View ZL2008ALAFT_4828518.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ZL2008
Data Sheet February 19, 2009 FN6859.0
Digital DC-DC Controller with Drivers and Pin-Strap Current Sharing
Description
The ZL2008 is a digital DC-DC controller with integrated MOSFET drivers. Current sharing allows multiple devices to be connected in parallel to source loads with very high current demands. Adaptive performance optimization algorithms improve power conversion efficiency. Zilker Labs Digital-DCTM technology enables a blend of power conversion performance and power management features. The ZL2008 is designed to be a flexible building block for DC power and can be easily adapted to designs ranging from a single-phase power supply operating from a 3.3 V input to a multi-phase supply operating from a 12 V input. The ZL2008 eliminates the need for complicated power supply managers as well as numerous external discrete components. Key operating features can be configured by pin-straps, including compensation, current sharing and output voltage. The ZL2008 uses the I2C/SMBusTM with PMBusTM protocol for communication with a host controller and the Digital-DC bus for communication between Zilker Labs devices.
Features
Power Conversion
Efficient synchronous buck controller Adaptive light load efficiency optimization 3 V to 14 V input range 0.54 V to 5.5 V output range (with margin) POLA and DOSA voltage trim modes 1% output voltage accuracy Internal 3 A MOSFET drivers Fast load transient response Current sharing and phase interleaving SnapshotTM parameter capture RoHS compliant (6 x 6 mm) QFN package
Power Management
Digital soft start / stop Precision delay and ramp-up Power good / enable Voltage tracking, sequencing and margining Voltage, current and temperature monitoring I2C/SMBus interface, PMBus compatible Output voltage and current protection Internal non-volatile memory (NVM)
Applications
Servers / storage equipment Telecom / datacom equipment Power supply modules
EN PG PH_EN FC ILIM CFG UVLO V25
VR VDD
V SS VTRK MGN SYNC DDC
LDO POWER MANAGEMENT DRIVER NONVOLATILE MEMORY PWM CONTROLLER BST GH SW GL VSEN+ VSENISENA ISENB
CURRENT SENSE TEMP SENSOR
SCL SDA SALRT
I2 C
MONITOR ADC
SA
XTEMP
PGND SGND DGND
Figure 1. Block Diagram
Figure 2. Efficiency vs. Load Current
1-888-INTERSIL or 1-888-468-3774|Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners
1
ZL2008
Table of Contents
1. Electrical Characteristics ...............................................................................................................................................4 2. Pin Descriptions ............................................................................................................................................................8 3. Typical Application Circuit.........................................................................................................................................10 4. ZL2008 Overview .......................................................................................................................................................11
4.1 Digital-DC Architecture ......................................................................................................................................................... 11 4.2 Power Conversion Overview.................................................................................................................................................. 12 4.3 Power Management Overview ............................................................................................................................................... 13 4.4 Multi-mode Pins..................................................................................................................................................................... 13
5. Power Conversion Functional Description..................................................................................................................15
5.1 Internal Bias Regulators and Input Supply Connections ........................................................................................................ 15 5.2 High-side Driver Boost Circuit .............................................................................................................................................. 15 5.3 Output Voltage Selection ....................................................................................................................................................... 15
5.3.1. Standard Mode..............................................................................................................................................15 5.3.2. SMBus Mode.................................................................................................................................................16 5.3.3. POLA Voltage Trim Mode ............................................................................................................................16 5.3.4. DOSA Voltage Trim Mode............................................................................................................................17
5.4 Start-up Procedure.................................................................................................................................................................. 17 5.5 Soft Start Delay and Ramp Times .......................................................................................................................................... 18 5.6 Power Good............................................................................................................................................................................ 19 5.7 Switching Frequency and PLL ............................................................................................................................................... 20 5.8 Power Train Component Selection......................................................................................................................................... 21
5.8.1. Design Goal Trade-offs ................................................................................................................................22 5.8.2. Inductor Selection.........................................................................................................................................22 5.8.3. Output Capacitor Selection ..........................................................................................................................23 5.8.4. Input Capacitor.............................................................................................................................................23 5.8.5. Bootstrap Capacitor Selection......................................................................................................................23 5.8.6. QL Selection..................................................................................................................................................23 5.8.7. QH Selection.................................................................................................................................................24 5.8.8. MOSFET Thermal Check .............................................................................................................................24 5.8.9. Current Sensing Components .......................................................................................................................24
5.9 Current Limit Threshold Selection......................................................................................................................................... 25 5.10 Loop Compensation ............................................................................................................................................................. 26 5.11 Non-linear Response (NLR) Settings ................................................................................................................................... 28 5.12 Efficiency Optimized Driver Dead-time Control ................................................................................................................. 28 5.13 Adaptive Diode Emulation................................................................................................................................................... 28 5.14 Adaptive Frequency Control ................................................................................................................................................ 28
6. Power Management Functional Description ...............................................................................................................30
6.1 Input Undervoltage Lockout .................................................................................................................................................. 30 6.2 Output Overvoltage Protection............................................................................................................................................... 30 6.3 Output Pre-Bias Protection..................................................................................................................................................... 30 6.4 Output Overcurrent Protection ............................................................................................................................................... 32 6.5 Thermal Overload Protection ................................................................................................................................................. 32 6.6 Voltage Tracking.................................................................................................................................................................... 32 6.7 Voltage Margining ................................................................................................................................................................. 34 6.8 I2C/SMBus Communications ................................................................................................................................................. 34 6.9 I2C/SMBus Device Address Selection ................................................................................................................................... 34 6.10 Digital-DC Bus..................................................................................................................................................................... 35 6.11 Phase Spreading ................................................................................................................................................................... 35 6.12 Output Sequencing ............................................................................................................................................................... 36 6.13 Fault Spreading .................................................................................................................................................................... 36 6.14 Temperature Monitoring Using the XTEMP Pin ................................................................................................................. 36 6.15 Active Current Sharing......................................................................................................................................................... 37 6.16 Phase Adding/Dropping ....................................................................................................................................................... 39 6.17 Monitoring via I2C/SMBus................................................................................................................................................... 40
2
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
6.18 Snapshot Parameter Capture ................................................................................................................................................ 40 6.19 Non-Volatile Memory and Device Security Features .......................................................................................................... 41
7. Pin-strap Current Sharing Configuration.....................................................................................................................42
7.1 SMBus Address (SA0, SA1 Pins) .......................................................................................................................................... 42 7.2 Current Share Pin-Straps (CFG0, CFG2 Pins) ....................................................................................................................... 42 7.3 SYNC Clock (CFG1 Pin) ....................................................................................................................................................... 42 7.4 Soft Start (SS Pin) .................................................................................................................................................................. 42 7.5 Phase Enable (PH_EN Pin) .................................................................................................................................................... 43 7.6 MFR_CONFIG Command ..................................................................................................................................................... 43 7.7 VOUT_DROOP Command.................................................................................................................................................... 43 7.8 Current Sharing Example ....................................................................................................................................................... 44
8. Package Dimensions....................................................................................................................................................45 9. Ordering Information ..................................................................................................................................................46 10. Related Tools and Documentation ............................................................................................................................46 11. Revision History........................................................................................................................................................46
3
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
1. Electrical Characteristics
Table 1. Absolute Maximum Ratings
Operating beyond these limits may cause permanent damage to the device. Functional operation beyond the Recommended Operating Conditions is not implied. Voltage measured with respect to SGND.
Parameter DC supply voltage MOSFET drive reference 2.5 V logic reference Pin VDD VR V25 CFG(0,1,2), DDC, EN, FC(0,1), ILIM, MGN, PG, PH_EN, SA(0,1), SALRT, SCL, SDA, SS, SYNC, UVLO, V(0,1) ISENB, VSEN, VTRK, XTEMP ISENA BST BST - SW GH GL SW SW DGND - SGND, PGND - SGND - - All Value - 0.3 to 17 - 0.3 to 6.5 120 - 0.3 to 3 120 - 0.3 to 6.5 - 0.3 to 6.5 - 1.5 to 30 - 0.3 to 30 - 0.3 to 8 (VSW-0.3) to (VBST+0.3) (PGND-0.3) to (VR+0.3) (PGND-0.3) to 30 (PGND-5) to 30 - 0.3 to 0.3 - 55 to 150 - 55 to 150 300 Unit V V mA V mA V V V V V V V V V V C C C
Logic I/O voltage
Analog input voltages High side supply voltage Boost to switch voltage High side drive voltage Low side drive voltage Switch node continuous Switch node transient (<100ns) Ground differential Junction temperature Storage temperature Lead temperature (Soldering, 10 s)
Table 2. Recommended Operating Conditions and Thermal Information Parameter Symbol Input supply voltage range, VDD (See Figure 9) Output voltage range
1
Min 3.0 4.5 0.54 - 40 -
Typ - - - - 35
Max 5.5 14 5.5 125 -
Unit V V V C C/W
VDD tied to VR
VR floating
VOUT TJ
2
Operating junction temperature range Junction to ambient thermal impedance
3
JA
Junction to case thermal impedance JC - 5 - C/W Notes: 1. Includes margin limits. 2. JA is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance ground plane using multiple vias. 3. For JC, the "case" temperature is measured at the center of the exposed metal pad.
4
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Table 3. Electrical Specifications
VDD = 12 V, TA = -40C to 85C unless otherwise noted. Typical values are at TA = 25C.
Parameter Input and Supply Characteristics IDD supply current at fSW = 200 kHz IDD supply current at fSW = 1.4 MHz IDDS shutdown current VR reference output voltage V25 reference output voltage Output Characteristics Output voltage adjustment range1 Output voltage set-point resolution Output voltage accuracy3 VSEN input bias current Current sense differential input voltage (ground referenced) Current sense differential input voltage (VOUT referenced, VOUT < 4.0 V) Current sense input bias current Current sense input bias current (VOUT referenced, VOUT < 4.0 V) Soft start delay duration range4 Soft start delay duration accuracy Soft start ramp duration range Conditions GH, GL no load; MISC_CONFIG[7] = 1 EN = 0 V No I2C/SMBus activity VDD > 6 V, IVR < 50 mA VR > 3 V, IV25 < 50 mA VIN > VOUT Set using resistors Set using I2C/SMBus Includes line, load, temp VSEN = 5.5 V VISENA - VISENB VISENA - VISENB Ground referenced ISENA ISENB Set using SS pin or resistor Set using I2C/SMBus Turn-on delay (precise mode) 4,5 Turn-on delay (normal mode) 6 Turn-off delay 6 Set using SS pin or resistor Set using I2C - - 2 0 - Min - - - 4.5 2.25 0.6 - - -1 - - 100 - 50 - 100 -1 - 100 2 0.002 Typ 16 25 6.5 5.2 2.5 - 10 0.025 - 110 - - - - - - - 0.25 - - -0.25/+4 -0.25/+4 - - 100 Max 30 50 8 5.5 2.75 5.0 - - 1 200 100 50 100 1 100 30 500 - - 20 200 - Unit mA mA mA V V V mV % FS2 % A mV mV A A A ms s ms ms ms ms ms s
Soft start ramp duration accuracy Notes: 1. Does not include margin limits. 2. Percentage of Full Scale (FS) with temperature compensation applied. 3. VOUT measured at the termination of the VSEN+ and VSEN- sense points. 4. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to approx 2 ms, where in normal mode it may vary up to 4 ms. 5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable. 6. The devices may require up to a 4 ms delay following the assertion of the enable signal (normal mode) or following the deassertion of the enable signal.
5
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Table 3. Electrical Characteristics (continued)
VDD = 12 V, TA = -40C to 85C unless otherwise noted. Typical values are at TA = 25C.
Conditions Parameter Logic Input/Output Characteristics Logic input bias current EN,PG,SCL,SDA,SALRT pins MGN input bias current Logic input low, VIL Multi-mode logic pins Logic input OPEN (N/C) Logic input high, VIH IOL 4 mA Logic output low, VOL IOH -2 mA Logic output high, VOH Oscillator and Switching Characteristics Switching frequency range Predefined settings Switching frequency set-point accuracy (See Table 15) Factory default Maximum PWM duty cycle Minimum SYNC pulse width External clock source Input clock frequency drift tolerance Gate Drivers High-side driver voltage (VBST - VSW) High-side driver peak gate drive (VBST - VSW) = 4.5 V current (pull down) High-side driver pull-up (VBST - VSW) = 4.5 V, resistance (VBST - VGH) = 50 mV High-side driver pull-down (VBST - VSW) = 4.5 V, resistance (VGH - VSW) = 50 mV Low-side driver peak gate drive VR = 5 V current (pull-up) Low-side driver peak gate drive VR = 5 V current (pull-down) Low-side driver pull-up VR = 5 V, resistance (VR - VGL) = 50 mV Low-side driver pull-down VR = 5 V, resistance (VGL - PGND) = 50 mV (VBST - VSW) = 4.5 V, Switching timing CLOAD = 2.2 nF GH rise and fall time VR = 5 V, GL rise and fall time CLOAD = 2.2 nF Tracking VTRK = 5.5 V VTRK input bias current 100% Tracking, VOUT - VTRK VTRK tracking ramp accuracy 100% Tracking, VOUT - VTRK VTRK regulation accuracy Min - 10 -1 - - 2.0 - 2.25 200 -5 95 150 - 13 Typ - - - 1.4 - - - - - - - - 4.5 3 0.8 0.5 2.5 1.8 1.2 0.5 5 5 110 - - Max 10 1 0.8 - - 0.4 - 1400 5 - - 13 Unit A mA V V V V V kHz % % ns % V A A A ns ns A mV %
- 2 - - - - - - - - - - 100 -1
- - 2 2 - - 2 2 20 20 200 + 100 1
6
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Table 3. Electrical Characteristics (continued)
VDD = 12 V, TA = -40C to 85C unless otherwise noted. Typical values are at TA = 25C.
Parameter Fault Protection Characteristics UVLO threshold range UVLO set-point accuracy UVLO hysteresis UVLO delay Power good VOUT low threshold Power good VOUT high threshold Power good VOUT hysteresis Power good delay VSEN undervoltage threshold VSEN overvoltage threshold VSEN undervoltage hysteresis VSEN undervoltage/ overvoltage fault response time Current limit set-point accuracy (VOUT referenced) Current limit set-point accuracy (Ground referenced) Current limit protection delay Temperature compensation of current limit protection threshold Thermal protection threshold (junction temperature) Factory default Configurable via I2C/SMBus Factory default Configurable via I2C/SMBus Factory default Configurable via I2C/SMBus Conditions Configurable via I2C/SMBus Factory default Configurable via I2C/SMBus Factory default Factory default Factory default Using pin-strap or resistor 7 Configurable via I2C/SMBus Factory default Configurable via I2C/SMBus Factory default Configurable via I2C/SMBus Factory default Configurable via I2C/SMBus Min 2.85 - 150 - 0 - - - - 0 0 - 0 - 0 - - 5 - - - 1 100 - - 40 - Typ - - 3 - - 90 115 5 - - 85 - 115 - 5 16 - 10 10 5 - 4400 125 - 15 Max 16 150 - 100 2.5 - - - 200 500 - 110 - 115 - - 60 - - - 32 12700 - 125 - Unit V mV % % s % VOUT % VOUT % ms s % VOUT % VOUT % VOUT % VOUT % VOUT s s % FS8 % FS8 tSW 9 tSW 9 ppm / C C C C
Thermal protection hysteresis Notes: 7. Factory default Power Good delay is set to the same value as the soft start ramp time. 8. Percentage of Full Scale (FS) with temperature compensation applied 9. tSW = 1/fSW, where fSW is the switching frequency.
7
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
2. Pin Descriptions
34 32 36 35 31 33 30 29 28
DGND SYNC SA0 SA1 ILIM CFG0 SCL SDA SALRT
PG CFG2 PH_EN EN CFG1 MGN DDC XTEMP V25
1 2 3 4 5 6 7 8 9 12 13 14 10 11 15 16 17 18 27 26
36-Pin QFN 6 x 6 mm
Exposed Paddle
Connect to SGND
25 24 23 22 21 20 19
VDD BST GH SW PGND GL VR ISENA ISENB
Figure 3. ZL2008 Pin Configurations (top view) Table 4. Pin Descriptions Pin Label Type1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DGND SYNC SA0 SA1 ILIM CFG0 SCL SDA SALRT FC0 FC1 V0 V1 UVLO SS PWR I/O,M2
I, M
I, M I, M I/O I/O O I I I, M I, M
Description Digital ground. Common return for digital signals. Connect to low impedance ground plane. Clock synchronization input. Used to set switching frequency of internal clock or for synchronization to external frequency reference. Serial address select pins. Used to assign unique SMBus address to each IC or to enable certain management features. Current limit select. Sets the overcurrent threshold voltage for ISENA and ISENB. Configuration pin. Used to setup current sharing and non-linear response. Serial clock. Connect to external host and/or to other ZL devices. Serial data. Connect to external host and/or to other ZL devices. Serial alert. Connect to external host if desired. Loop compensation configuration pins. Output voltage selection pins. Used to set VOUT set-point and VOUT max. Undervoltage lockout selection. Sets the minimum value for VDD voltage to enable VOUT. Soft start pin. Sets the output voltage ramp time during turn-on and turn-off. Sets the delay from when EN is asserted until the output voltage starts to ramp. Tracking sense input. Used to track an external voltage source. Output voltage feedback. Connect to output regulation point.
VTRK I 16 VSEN+ I 17 Notes: 1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. 2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
8
FC0 FC1 V0 V1 UVLO SS VTRK VSEN+ VSEN-
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Table 4. Pin Descriptions (continued) Pin Label Type1 Description VSENI 18 Output voltage feedback. Connect to load return or ground regulation point. ISENB I Differential voltage input for current limit. 19 ISENA I Differential voltage input for current limit. High voltage tolerant. 20 VR PWR 21 Internal 5V reference used to power internal drivers. GL O Low side FET gate drive. 22 PGND PWR Power ground. Connect to low impedance ground plane. 23 SW PWR 24 Drive train switch node. GH O High-side FET gate drive. 25 BST PWR High-side drive boost voltage. 26 PWR Supply voltage. VDD3 27 V25 PWR Internal 2.5 V reference used to power internal circuitry. 28 29 30 31 32 33 34 35 36 ePad XTEMP DDC MGN CFG1 EN PH_EN CFG2 PG SGND I I/O I I, M I I I, M O PWR External temperature sensor input. Connect to external 2N3904 diode connected transistor. Digital-DC Bus. (Open Drain) Interoperability between Zilker Labs devices. Signal that enables margining of output voltage. Configuration pin. Used to setup clock synchronization and sequencing. Enable input (active high). Pull-up to enable PWM switching and pull-down to disable PWM switching. Phase enable input (active high). Pull-up to enable phase and pull-down to disable phase for current sharing. Configuration pin. Sets the phase offset (single-phase) or current sharing group position (multi-phase). Power good output. Exposed thermal pad. Common return for analog signals; internal connection to SGND. Connect to low impedance ground plane.
Notes: 1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. Please refer to Section 4.4"Multi-mode Pins," on page 13. 2. The SYNC pin can be used as a logic pin, a clock input or a clock output. 3. VDD is measured internally and the value is used to modify the PWM loop gain.
9
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
3. Typical Application Circuit
The following application circuit represents a typical implementation of the ZL2008. For PMBus operation, it is recommended to tie the enable pin (EN) to SGND.
VIN 12V CIN 3 x 10 F 25 V
F.B.1
ENABLE PHASE ENABLE POWER GOOD OUTPUT DDC Bus 3 CV25 10 F 4V QH DB BAT54
VDD BST GH SW
4.7 F 25 V
CFG2
CFG1
V25
1 DGND 2 SYNC 3 SA0 4 SA1 5 ILIM
XTEMP
PH_EN
MGN
DDC
V25
1 F 16 V CB LOUT 2.2 H COUT 2 x 47 F 6.3 V QL CVR VOUT
36
35
34
33
32
31
30
29
PG
EN
28
27 26 25 24 23 22 21 20 19
ZL2008
PGND GL VR ISENA
I2C/SMBus 2
6 CFG0 7 SCL 8 SDA 17 VSEN+ 18 VSEN14 UVLO 16 VRTK 9 SALRT 10 FC0 11 FC1 12 V0 13 V1
470 F 2.5 V
POS-CAP
ISENB
2*220 F 6.3 V 100 m RTN
15 SS
EPAD
SGND
4.7 F
6.3 V
Ground unification
Notes: 1. Ferrite bead is optional for input noise suppression 2. The I2C/SMBus requires pull-up resistors. Please refer to the I2C/SMBus specifications for more details. 3. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices connected). The 10 k default value, assuming a maximum of 100 pF per device, provides the necessary 1 s pull-up rise time. Please refer to the DDC Bus section for more details.
Figure 4. 12 V to 1.8 V / 16 A Application Circuit
10
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
4. ZL2008 Overview
4.1 Digital-DC Architecture
The ZL2008 is an innovative mixed-signal power conversion and power management IC based on Zilker Labs patented Digital-DC technology that provides an integrated, high performance step-down converter for a wide variety of power supply applications. Today's embedded power systems are typically designed for optimal efficiency at maximum load, reducing the peak thermal stress by limiting the total thermal dissipation inside the system. Unfortunately, many of these systems are often operated at load levels far below the peak where the power system has been optimized, resulting in reduced efficiency. While this may not cause thermal stress to occur, it does contribute to higher electricity usage and results in higher overall system operating costs. Zilker Labs' efficiency-adaptive ZL2008 DC-DC controller helps mitigate this scenario by enabling the power converter to automatically change their operating state to increase efficiency and overall performance with little or no user interaction needed. Its unique PWM loop utilizes an ideal mix of analog and digital blocks to enable precise control of the entire power conversion process with no software required, resulting in a very flexible device that is also very easy to use. An extensive set of power management functions are fully integrated and can be configured using simple pin connections. The user configuration can be saved in an internal non-volatile memory (NVM). Additionally, all functions can be configured and monitored via the SMBus hardware interface using
standard PMBus flexibility.
commands,
allowing
ultimate
Once enabled, the ZL2008 is immediately ready to regulate power and perform power management tasks with no programming required. Advanced configuration options and real-time configuration changes are available via the I2C/SMBus interface if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. Integrated subregulation circuitry enables single supply operation from any supply between 3 V and 14 V with no secondary bias supplies needed. The ZL2008 can be configured by simply connecting its pins according to the tables provided in the following sections. Additionally, a comprehensive set of online tools and application notes are available to help simplify the design process. An evaluation board is also available to help the user become familiar with the device. This board can be evaluated as a standalone platform using pin configuration settings. A WindowsTM-based GUI is also provided to enable full configuration and monitoring capability via the I2C/SMBus interface using an available computer and the included USB cable. Application notes and reference designs are available to assist the user in designing to specific application demands. Please register for My ZL on www.zilkerlabs.com to access the most up-to-date documentation or call your local Zilker Labs sales office to order an evaluation kit.
11
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
4.2 Power Conversion Overview
>
PG EN MGN
Input Voltage Bus
CFG(0,1,2) ILIM SS
V(0,1)
FC(0,1)
VDD
VR
VTRK
Power Management
NVM MOSFET Drivers D-PWM
NLR
BST
SYNC GEN
Digital Compensator
SW
VOUT
SYNC
PLL ADC ADC
+
-
VSEN ISENB ISENA
REFCN
DDC SALRT SDA SCL SA(0,1)
DAC
VDD
MUX
I2C
ADC Communication
Voltage Sensor TEMP Sensor
VSEN+ VSENXTEMP
Figure 5. ZL2008 Block Diagram
The ZL2008 operates as a voltage-mode, synchronous buck converter with a selectable constant frequency pulse width modulator (PWM) control scheme that uses external MOSFETs, capacitors, and an inductor to perform power conversion.
amount of time that QH is on as a fraction of the total switching period is known as the duty cycle D, which is described by the following equation:
D
VOUT VIN
During time D, QH is on and VIN - VOUT is applied across the inductor. The current ramps up as shown in Figure 7. When QH turns off (time 1-D), the current flowing in the inductor must continue to flow from the ground up through QL, during which the current ramps down. Since the output capacitor COUT exhibits a low impedance at the switching frequency, the AC component of the inductor current is filtered from the output voltage so the load sees nearly a DC voltage.
Figure 6. Synchronous Buck Converter
Figure 6 illustrates the basic synchronous buck converter topology showing the primary power train components. This converter is also called a step-down converter, as the output voltage must always be lower than the input voltage. In its most simple configuration, the ZL2008 requires two external N-channel power MOSFETs, one for the top control MOSFET (QH) and one for the bottom synchronous MOSFET (QL). The
12
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
The ZL2008 has several features to improve the power conversion efficiency. A non-linear response (NLR) loop improves the response time and reduces the output deviation as a result of a load transient. The ZL2008 monitors the power converter's operating conditions and continuously adjusts the turn-on and turn-off timing of the high-side and low-side MOSFETs to optimize the overall efficiency of the power supply. Adaptive performance optimization algorithms such as dead-time control, diode emulation, and frequency control are available to provide greater efficiency improvement.
4.3 Power Management Overview
VIN - VOUT ILPK
0
IO
ILV -VOUT
D
1-D
Time
Figure 7. Inductor Waveform
Typically, buck converters specify a maximum duty cycle that effectively limits the maximum output voltage that can be realized for a given input voltage. This duty cycle limit ensures that the lowside MOSFET is allowed to turn on for a minimum amount of time during each switching cycle, which enables the bootstrap capacitor (CB in Figure 6) to be charged up and provide adequate gate drive voltage for the highside MOSFET. See Section 5.2, "High-side Driver Boost Circuit," for more details. In general, the size of components L1 and COUT as well as the overall efficiency of the circuit are inversely proportional to the switching frequency, fSW. Therefore, the highest efficiency circuit may be realized by switching the MOSFETs at the lowest possible frequency; however, this will result in the largest component size. Conversely, the smallest possible footprint may be realized by switching at the fastest possible frequency but this gives a somewhat lower efficiency. Each user should determine the optimal combination of size and efficiency when determining the switching frequency for each application. The block diagram for the ZL2008 is illustrated in Figure 5. In this circuit, the target output voltage is regulated by connecting the differential VSEN pins directly to the output regulation point. The VSEN signal is then compared to a reference voltage that has been set to the desired output voltage level by the user. The error signal derived from this comparison is converted to a digital value with a low-resolution, analog to digital (A/D) converter. The digital signal is applied to an adjustable digital compensation filter, and the compensated signal is used to derive the appropriate PWM duty cycle for driving the external MOSFETs in a way that produces the desired output.
The ZL2008 incorporates a wide range of configurable power management features that are simple to implement with no external components. Additionally, the ZL2008 includes circuit protection features that continuously safeguard the device and load from damage due to unexpected system faults. The ZL2008 can continuously monitor input voltage, output voltage/current, internal temperature, and the temperature of an external thermal diode. A Power Good output signal is also included to enable power-on reset functionality for an external processor. All power management functions can be configured using either pin configuration techniques (see Figure 8) or via the I2C/SMBus interface. Monitoring parameters can also be pre-configured to provide alerts for specific conditions. See Application Note AN33 for more details on SMBus monitoring.
4.4 Multi-mode Pins
In order to simplify circuit design, the ZL2008 incorporates patented multi-mode pins that allow the user to easily configure many aspects of the device with no programming. Most power management features can be configured using these pins. The multimode pins can respond to four different connections as shown in Table 5. These pins are sampled when power is applied or by issuing a PMBus Restore command (See Application Note AN33). Pin-strap Settings: This is the simplest implementation method, as no external components are required. Using this method, each pin can take on one of three possible states: LOW, OPEN, or HIGH. These pins can be connected to the V25 pin for logic HIGH settings as this pin provides a regulated voltage higher than 2 V. Using a single pin, one of three settings can be
Data Sheet Revision 2/19/2009 www.intersil.com
13
ZL2008
selected. Using two pins, one of nine settings can be selected.
Table 5. Multi-mode Pin Configuration Pin Tied To LOW (Logic LOW) OPEN (N/C) HIGH (Logic HIGH) Resistor to SGND Value < 0.8 VDC No connection > 2.0 VDC Set by resistor value
Resistor Settings: This method allows a greater range of adjustability when connecting a finite value resistor (in a specified range) between the multi-mode pin and SGND. Standard 1% resistor values are used, and only every fourth E96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. Up to 31 unique selections are available using a single resistor. I2C/SMBus Method: Almost any ZL2008 function can be configured via the I2C/SMBus interface using standard PMBus commands. Additionally, any value that has been configured using the pin-strap or resistor setting methods can also be re-configured and/or verified via the I2C/SMBus. See Application Note AN33 for more details. The SMBus device address and VOUT_MAX are the only parameters that must be set by external pins. All other device parameters can be set via the I2C/SMBus. The device address is set using the SA0 and SA1 pins. VOUT_MAX is determined as 10% greater than the voltage set by the V0 and V1 pins.
Figure 8. Pin-strap and Resistor Setting Examples
14
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
5. Power Conversion Functional Description
5.1 Internal Bias Regulators and Input Supply Connections 5.2 High-side Driver Boost Circuit
The ZL2008 employs two internal low dropout (LDO) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. The internal bias regulators are as follows: VR: The VR LDO provides a regulated 5 V bias supply for the MOSFET driver circuits. It is powered from the VDD pin. A 4.7 F filter capacitor is required at the VR pin. V25: The V25 LDO provides a regulated 2.5 V bias supply for the main controller circuitry. It is powered from an internal 5V node. A 10 F filter capacitor is required at the V25 pin. When the input supply (VDD) is higher than 5.5 V, the VR pin should not be connected to any other pins. It should only have a filter capacitor attached as shown in Figure 9. Due to the dropout voltage associated with the VR bias regulator, the VDD pin must be connected to the VR pin for designs operating from a supply below 5.5 V. Figure 9 illustrates the required connections for both cases.
The gate drive voltage for the high-side MOSFET driver is generated by a floating bootstrap capacitor, CB (see Figure 6). When the lower MOSFET (QL) is turned on, the SW node is pulled to ground and the capacitor is charged from the internal VR bias regulator through diode DB. When QL turns off and the upper MOSFET (QH) turns on, the SW node is pulled up to VDD and the voltage on the bootstrap capacitor is boosted approximately 5 V above VDD to provide the necessary voltage to power the high-side driver. A Schottky diode should be used for DB to help maximize the high-side drive supply voltage.
5.3 Output Voltage Selection 5.3.1. Standard Mode
The output voltage may be set to any voltage between 0.6 V and 5.0 V provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding its maximum duty cycle specification. Using the pin-strap method, VOUT can be set to any of nine standard voltages as shown in Table 6.
Table 6. Output Voltage Pin-strap Settings V0 LOW OPEN LOW 0.6 V 0.8 V V1 OPEN 1.2 V 1.5 V HIGH 2.5 V 3.3 V
HIGH 1.0 V 1.8 V 5.0 V
Figure 9. Input Supply Connections
Note: the internal bias regulators are not designed to be outputs for powering other circuitry. Do not attach external loads to any of these pins. The multi-mode pins may be connected to the V25 pin for logic HIGH settings.
The resistor setting method can be used to set the output voltage to levels not available in Table 6. Resistors R0 and R1 are selected to produce a specific voltage between 0.6 V and 5.0 V in 10 mV steps. Resistor R1 provides a coarse setting and resistor R0 provides a fine adjustment, thus eliminating the additional errors associated with using two 1% resistors (this typically adds approx 1.4% error).
15
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
To set VOUT using resistors, follow the steps below to calculate an index value and then use Table 7 to select the resistor that corresponds to the calculated index value as follows: 1. Calculate Index1: Index1 = 4 x VOUT (VOUT in 10 mV steps) 2. Round the result down to the nearest whole number. 3. Select the value of R1 from Table 7 using the Index1 rounded value from step 2. 4. Calculate Index0: Index0 = 100 x VOUT - (25 x Index1) 5. Select the value of R0 from Table 7 using the Index0 value from step 4.
Table 7. Output Voltage Resistors Settings Index R0 or R1 Index R0 or R1 0 13 10 k 34.8 k 1 14 11 k 38.3 k 2 15 12.1 k 42.2 k 3 16 13.3 k 46.4 k 4 17 14.7 k 51.1 k 5 18 16.2 k 56.2 k 6 19 17.8 k 61.9 k 7 20 19.6 k 68.1 k 8 21 21.5 k 75 k 9 22 23.7 k 82.5 k 10 23 26.1 k 90.9 k 11 24 28.7 k 100 k 12 31.6 k Figure 10. Output Voltage Resistor Setting Example 5.3.3. POLA Voltage Trim Mode
The output voltage mapping can be changed to match the voltage setting equations for POLA and DOSA standard modules. The standard method for adjusting the output voltage for a POLA module is defined by the following equation:
RSET = 10k x
0.69V - 1.43k VOUT - 0.69V
The resistor, RSET, is external to the POLA module. See Figure 11.
Example from Figure 10: For VOUT = 1.33 V, Index1 = 4 x 1.33 V = 5.32; From Table 7, R1 = 16.2 k Index0 = (100 x 1.33 V) - (25 x 5) = 8; From Table 7, R0 = 21.5 k
Figure 11. Output Voltage Setting on POLA Module 5.3.2. SMBus Mode
The output voltage may be set to any value between 0.6 V and 5.0 V using a PMBus command over the I2C/SMBus interface. See Application Note AN33 for details.
To stay compatible with this existing method for adjusting the output voltage and to keep the same external RSET resistor when using the ZL2008, the module manufacturer should add a 10k resistor on the module as shown in Figure 12. Now, the same RSET used for an analog POLA module will provide the same output voltage when using a digital POLA module based on the ZL2008.
16
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
To maintain DOSA compatibility, the same scheme is used as with a POLA module except the 10 k resistor is replaced with a 8.66 k resistor as shown in Figure 13.
DOSA MODULE
ZL
V0 V1
110 k
8.66 k
Figure 12. RSET on a POLA Module
Rset
The POLA mode is activated through pin-strap by connecting a 110 k resistor on V0 to SGND. The V1 pin is then used to adjust the output voltage as shown in Table 8. The POLA mode can also be activated through PMBus commands. See Application Note AN33 for more details.
Table 8. POLA Mode VOUT Settings
Figure 13. RSET on a DOSA Module
The DOSA mode VOUT settings are listed in Table 9.
Table 9. DOSA Mode VOUT Settings
(R0 = 110 k, R1 = RSET + 8.66 k)
VOUT 0.700 V 0.752 V 0.758 V 0.765 V 0.772 V 0.790 V 0.800 V 0.821 V 0.834 V 0.848 V 0.880 V 0.899 V 0.919 V 0.965 V
In series with 8.66k resistor
RSET
VOUT 0.991 V 1.000 V 1.100 V 1.158 V 1.200 V 1.250 V 1.500 V 1.669 V 1.800 V 2.295 V 2.506 V 3.300 V 5.000 V
In series with 8.66k resistor
RSET
(R0 = 110 k, R1 = RSET + 10 k)
VOUT 0.700 V 0.752 V 0.758 V 0.765 V 0.772 V 0.790 V 0.800 V 0.821 V 0.834 V 0.848 V 0.880 V 0.899 V 0.919 V 0.965 V
In series with 10k resistor
RSET
VOUT 0.991 V 1.000 V 1.100 V 1.158 V 1.200 V 1.250 V 1.500 V 1.669 V 1.800 V 2.295 V 2.506 V 3.300 V 5.000 V
In series with 10k resistor
RSET
162 k 110 k 100 k 90.9 k 82.5 k 75.0 k 56.2 k 51.1 k 46.4 k 42.2 k 34.8 k 31.6 k 28.7 k 23.7 k
21.5 k 19.6 k 16.2 k 13.3 k 12.1 k 9.09 k 7.50 k 5.62 k 4.64 k 2.87 k 2.37 k 1.21 k 0.162 k
162 k 113 k 100 k 90.9 k 82.5 k 75.0 k 57.6 k 52.3 k 47.5 k 43.2 k 36.5 k 33.2 k 30.1 k 25.5 k
22.6 k 21.0 k 17.8 k 14.7 k 13.3 k 10.5 k 8.87 k 6.98 k 6.04 k 4.32 k 3.74 k 2.61 k 1.50 k
5.4 Start-up Procedure
The ZL2008 follows a specific internal start-up procedure after power is applied to the VDD pin. Table 10 describes the start-up sequence. If the device is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the EN pin. The device requires approximately 5-10 ms to check for specific values stored in its internal memory. If the user has stored values in memory, those values will be loaded. The device will then check the status of all multi-mode pins and load the values associated with the pin settings.
Data Sheet Revision 2/19/2009 www.intersil.com
5.3.4. DOSA Voltage Trim Mode
On a DOSA module, the VOUT setting follows this equation:
RSET =
6900 VOUT - 0.69V
17
ZL2008
Once this process is completed, the device is ready to accept commands via the I2C/SMBus interface and the device is ready to be enabled. Once enabled, the device requires approximately 2 ms before its output voltage may be allowed to start its ramp-up process. If a softstart delay period less than 2 ms has been configured (using PMBus commands), the device will default to a 2 ms delay period. If a delay period greater than 2 ms is configured, the device will wait for the configured delay period prior to starting to ramp its output. After the delay period has expired, the output will begin to ramp towards its target voltage according to the pre-configured soft-start ramp time that has been set using the SS pin. It should be noted that if the EN pin is tied to VDD, the device will still require approx 5-10 ms before the output can begin its ramp-up as described in Table 10 below.
5.5 Soft Start Delay and Ramp Times
These features may be used as part of an overall inrush current management strategy or to precisely control how fast a load IC is turned on. The ZL2008 gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. The soft-start delay period begins when the EN pin is asserted and ends when the delay time expires. The soft-start delay period is set using the SS pin. Precise ramp delay timing reduces the delay time variations but is only available when the appropriate bit in the MISC_CONFIG register has been set. Please refer to Application Note AN33 for details. The soft-start ramp timer enables a precisely controlled ramp to the nominal VOUT value that begins once the delay period has expired. The ramp-up is guaranteed monotonic and its slope may be precisely set using the SS pin. The soft start delay and ramp times can be set to standard values according to Table 11.
It may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. In addition, the designer may wish to precisely set the time required for VOUT to ramp to its target value after the delay period has expired.
Table 10. ZL2008 Start-up Sequence Step # Step Name 1 2 3 4 5 Power Applied Internal Memory Check Multi-mode Pin Check Device Ready Pre-ramp Delay
Description
Input voltage is applied to the ZL2008's VDD pin The device will check for values stored in its internal memory. This step is also performed after a Restore command. The device loads values configured by the multi-mode pins. The device is ready to accept an enable signal. The device requires approximately 2 ms following an enable signal and prior to ramping its output. Additional pre-ramp delay may be configured using the SS pin.
Time Duration Depends on input supply ramp time Approx 5-10 ms (device will ignore an enable signal or PMBus traffic during this period) Approximately 2 ms
18
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Table 11. Soft Start Pin-strap Settings Delay Time SS Pin Ramp Time 2 ms LOW 2 ms 5 ms OPEN 5 ms 10 ms HIGH 10 ms Table 12. SS Resistor Settings Delay Time RSS 10 k 2 ms 11 k 12.1 k 13.3 k 14.7 k 5 ms 16.2 k 17.8 k 19.6 k 21.5 k 10 ms 23.7 k 26.1 k 28.7 k 31.6 k 15 ms 34.8 k 38.3 k 42.2 k 46.4 k 20 ms 51.1 k 56.2 k 61.9 k 68.1 k 30 ms 75 k 82.5 k 5.6 Power Good Ramp Time 5 ms 10 ms 20 ms 2 ms 5 ms 10 ms 20 ms 2 ms 5 ms 10 ms 20 ms 2 ms 5 ms 10 ms 20 ms 2 ms 5 ms 10 ms 20 ms 2 ms 5 ms 10 ms 20 ms
If the desired soft start delay and ramp times are not one of the values listed in Table 11, the times can be set to a custom value by connecting a resistor from the SS pin to SGND using the appropriate resistor value from Table 12. The value of this resistor is measured upon start-up or Restore and will not change if the resistor is varied after power has been applied to the ZL2008. See Figure 14 for typical connections using resistors.
ZL
RSS
Figure 14. SS Pin Resistor Connections
The soft start delay and ramp times can also be set to custom values via the I2C/SMBus interface. When the SS delay time is set to 0 ms, the device will begin its ramp-up after the internal circuitry has initialized (approx. 2 ms). When the soft-start ramp period is set to 0 ms, the output will ramp up as quickly as the output load capacitance and loop settings will allow. It is generally recommended to set the soft-start ramp to a value greater than 500 s to prevent inadvertent fault conditions due to excessive inrush current.
The ZL2008 provides a Power Good (PG) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. By default, the PG pin will assert if the output is within -10%/+15% of the target voltage. These limits and the polarity of the pin may be changed via the I2C/SMBus interface. See Application Note AN33 for details. A PG delay period is defined as the time from when all conditions within the ZL2008 for asserting PG are met to when the PG pin is actually asserted. This feature is commonly used instead of using an external reset controller to control external digital logic. By default, the ZL2008 PG delay is set equal to the soft-start ramp time setting. Therefore, if the soft-start ramp time is set to 10 ms, the PG delay will be set to 10 ms. The PG delay may be set independently of the soft-start ramp using the I2C/SMBus as described in Application Note AN33.
19
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
5.7 Switching Frequency and PLL
Configuration C: SYNC AUTO DETECT When the SYNC pin is configured in auto detect mode (CFG1 pin is left OPEN), the device will automatically check for a clock signal on the SYNC pin after enable is asserted. If a clock signal is present, The ZL2008's oscillator will then synchronize the rising edge of the external clock. Refer to SYNC INPUT description. If no incoming clock signal is present, the ZL2008 will configure the switching frequency according to the state of the SYNC pin as listed in Table 14. In this mode, the ZL2008 will only read the SYNC pin connection during the start-up sequence. Changes to SYNC pin connections will not affect fSW until the power (VDD) is cycled off and on.
Table 14. Switching Frequency Pin-strap Settings SYNC Pin Frequency LOW 200 kHz OPEN 400 kHz HIGH 1 MHz Resistor See Table 15
The ZL2008 incorporates an internal phase-locked loop (PLL) to clock the internal circuitry. The PLL can be driven by an external clock source connected to the SYNC pin. When using the internal oscillator, the SYNC pin can be configured as a clock source for other Zilker Labs devices. The SYNC pin is a unique pin that can perform multiple functions depending on how it is configured. The CFG1 pin is used to select the operating mode of the SYNC pin as shown in Table 13. Figure 15 illustrates the typical connections for each mode.
Table 13. SYNC Pin Function Selection CFG1 Pin SYNC Pin Function LOW SYNC is configured as an input OPEN Auto Detect mode SYNC is configured as an output HIGH fSW = 400 kHz
Configuration A: SYNC OUTPUT When the SYNC pin is configured as an output (CFG1 pin is tied HIGH), the device will run from its internal oscillator and will drive the resulting internal oscillator signal (preset to 400 kHz) onto the SYNC pin so other devices can be synchronized to it. The SYNC pin will not be checked for an incoming clock signal while in this mode. Configuration B: SYNC INPUT When the SYNC pin is configured as an input (CFG1 pin is tied LOW), the device will automatically check for a clock signal on the SYNC pin each time EN is asserted. The ZL2008's oscillator will then synchronize with the rising edge of the external clock. The incoming clock signal must be in the range of 200 kHz to 1.4 MHz and must be stable when the enable pin is asserted. The clock signal must also exhibit the necessary performance requirements (see Table 3). In the event of a loss of the external clock signal, the output voltage may show transient over/undershoot. If this happens, the ZL2008 will automatically switch to its internal oscillator and switch at a frequency close to the previous incoming frequency.
If the user wishes to run the ZL2008 at a frequency not listed in Table 14, the switching frequency can be set using an external resistor, RSYNC, connected between SYNC and SGND using Table 15.
20
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
CFG1
CFG1
CFG1
CFG1
Figure 15. SYNC Pin Configurations Table 15. Switching Frequency Resistor Settings RSYNC fSW RSYNC fSW 200 kHz 533 kHz 10 k 26.1 k 222 kHz 571 kHz 11 k 28.7 k 242 kHz 615 kHz 12.1 k 31.6 k 267 kHz 727 kHz 13.3 k 34.8 k 296 kHz 800 kHz 14.7 k 38.3 k 320 kHz 889 kHz 16.2 k 46.4 k 364 kHz 1000 kHz 17.8 k 51.1 k 400 kHz 1143 kHz 19.6 k 56.2 k 421 kHz 1333 kHz 21.5 k 68.1 k 471 kHz 23.7 k
Note: The switching frequency read back using the appropriate PMBus command will differ slightly from the selected values in Table 15. The difference is due to hardware quantization.
5.8 Power Train Component Selection
The ZL2008 is a synchronous buck converter that uses external MOSFETs, inductor and capacitors to perform the power conversion process. The proper selection of the external components is critical for optimized performance. To select the appropriate external components for the desired performance goals, the power supply requirements listed in Table 16 must be known.
The switching frequency can also be set to any value between 200 kHz and 1.33 MHz using the I2C/SMBus interface. The available frequencies below 1.4 MHz are defined by fSW = 8 MHz/N, where the whole number N is 6 N 40. See Application Note AN33 for details. If a value other than fSW = 8 MHz/N is entered using a PMBus command, the internal circuitry will select the valid switching frequency value that is closest to the entered value. For example, if 810 kHz is entered, the device will select 800 kHz (N=10). When multiple Zilker Labs devices are used together, connecting the SYNC pins together will force all devices to synchronize with each other. The CFG1 pin of one device must set its SYNC pin as an output and the remaining devices must have their SYNC pins set as Auto Detect.
21
Data Sheet Revision 2/19/2009 www.intersil.com
CFG1
ZL2008
Table 16. Power Supply Requirements
Parameter Input voltage (VIN) Output voltage (VOUT) Output current (IOUT) Output voltage ripple (Vorip) Output load step (Iostep) Output load step rate Output deviation due to load step Maximum PCB temp. Desired efficiency Other considerations Range 3.0 - 14.0 V 0.6 - 5.0 V 0 to ~25 A < 3% of VOUT < Io -- -- 120C -- Various Example Value 12 V 1.2 V 20 A 1% of VOUT 50% of Io 10 A/S 50 mV 85C 85% Optimize for small size
between output ripple and optimal load transient performance. A good starting point is to select the output inductor ripple equal to the expected load transient step magnitude (Iostep):
I opp = I ostep
Now the output inductance can be calculated using the following equation, where VINM is the maximum input voltage:
LOUT
V VOUT x 1 - OUT V INM = fsw x I opp

5.8.1. Design Goal Trade-offs
The average inductor current is equal to the maximum output current. The peak inductor current (ILpk) is calculated using the following equation where IOUT is the maximum output current:
The design of the buck power stage requires several compromises among size, efficiency, and cost. The inductor core loss increases with frequency, so there is a trade-off between a small output filter made possible by a higher switching frequency and getting better power supply efficiency. Size can be decreased by increasing the switching frequency at the expense of efficiency. Cost can be minimized by using throughhole inductors and capacitors; however these components are physically large. To start the design, select a switching frequency based on Table 17. This frequency is a starting point and may be adjusted as the design progresses.
Table 17. Circuit Design Considerations Frequency Range 200-400 kHz 400-800 kHz 800 kHz - 1.4 MHz 5.8.2. Inductor Selection Efficiency Highest Moderate Lower Circuit Size Larger Smaller Smallest
I Lpk = I OUT +
I opp
2
Select an inductor rated for the average DC current with a peak current rating above the peak current computed above. In over-current or short-circuit conditions, the inductor may have currents greater than 2X the normal maximum rated output current. It is desirable to use an inductor that still provides some inductance to protect the load and the MOSFETs from damaging currents in this situation. Once an inductor is selected, the DCR and core losses in the inductor are calculated. Use the DCR specified in the inductor manufacturer's datasheet.
PLDCR = DCR x I Lrms
ILrms is given by
2
I Lrms = I OUT +
2
(I )
opp
2
12
The output inductor selection process must include several trade-offs. A high inductance value will result in a low ripple current (Iopp), which will reduce output capacitance and produce a low output ripple voltage, but may also compromise output transient load performance. Therefore, a balance must be struck
where IOUT is the maximum output current. Next, calculate the core loss of the selected inductor. Since this calculation is specific to each inductor and manufacturer, refer to the chosen inductor datasheet. Add the core loss and the ESR loss and compare the total loss to the maximum power dissipation recommendation in the inductor datasheet.
22
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
5.8.3. Output Capacitor Selection
Several trade-offs must also be considered when selecting an output capacitor. Low ESR values are needed to have a small output deviation during transient load steps (Vosag) and low output voltage ripple (Vorip). However, capacitors with low ESR, such as semi-stable (X5R and X7R) dielectric ceramic capacitors, also have relatively low capacitance values. Many designs can use a combination of high capacitance devices and low ESR devices in parallel. For high ripple currents, a low capacitance value can cause a significant amount of output voltage ripple. Likewise, in high transient load steps, a relatively large amount of capacitance is needed to minimize the output voltage deviation while the inductor current ramps up or down to the new steady state output current value. As a starting point, apportion one-half of the output ripple voltage to the capacitor ESR and the other half to capacitance, as shown in the following equations:
(ICINrms) can be determined from the following equation:
I CINrms = I OUT x D x (1 - D )
Without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. The input capacitors should be rated at 1.2X the ripple current calculated above to avoid overheating of the capacitors due to the high ripple current, which can cause premature failure. Ceramic capacitors with X7R or X5R dielectric with low ESR and 1.1X the maximum expected input voltage are recommended.
5.8.5. Bootstrap Capacitor Selection
C OUT =
I opp 8 x f sw x Vorip 2
The high-side driver boost circuit utilizes an external Schottky diode (DB) and an external bootstrap capacitor (CB) to supply sufficient gate drive for the high-side MOSFET driver. DB should be a 20 mA, 30 V Schottky diode or equivalent device and CB should be a 1 F ceramic type rated for at least 6.3V.
5.8.6. QL Selection
ESR =
Vorip 2 x I opp
The bottom MOSFET should be selected primarily based on the device's RDS(ON) and secondarily based on its gate charge. To choose QL, use the following equation and allow 2-5% of the output power to be dissipated in the RDS(ON) of QL (lower output voltages and higher step-down ratios will be closer to 5%):
Use these values to make an initial capacitor selection, using a single capacitor or several capacitors in parallel. After a capacitor has been selected, the resulting output voltage ripple can be calculated using the following equation:
PQL = 0.05 x VOUT x I OUT
Calculate the RMS current in QL as follows:
I botrms = I Lrms x 1 - D
Calculate the desired maximum RDS(ON) as follows:
Vorip = I opp x ESR +
I opp 8 x f sw x C OUT
RDS ( ON ) =
(I botrms )2
PQL
Because each part of this equation was made to be less than or equal to half of the allowed output ripple voltage, the Vorip should be less than the desired maximum output ripple.
5.8.4. Input Capacitor
It is highly recommended that dedicated input capacitors be used in any point-of-load design, even when the supply is powered from a heavily filtered 5 or 12 V "bulk" supply from an off-line power supply. This is because of the high RMS ripple current that is drawn by the buck converter topology. This ripple
Note that the RDS(ON) given in the manufacturer's datasheet is measured at 25C. The actual RDS(ON) in the end-use application will be much higher. For example, a Vishay Si7114 MOSFET with a junction temperature of 125C has an RDS(ON) that is 1.4 times higher than the value at 25C. Select a candidate MOSFET, and calculate the required gate drive current as follows:
I g = f SW x Qg
23
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Keep in mind that the total allowed gate drive current for both QH and QL is 80 mA. MOSFETs with lower RDS(ON) tend to have higher gate charge requirements, which increases the current and resulting power required to turn them on and off. Since the MOSFET gate drive circuits are integrated in the ZL2008, this power is dissipated in the ZL2008 according to the following equation:
5.8.8. MOSFET Thermal Check
Once the power dissipations for QH and QL have been calculated, the MOSFETs junction temperature can be estimated. Using the junction-to-case thermal resistance (Rth) given in the MOSFET manufacturer's datasheet and the expected maximum printed circuit board temperature, calculate the junction temperature as follows:
PQL = f sw x Qg x VINM
5.8.7. QH Selection
T j max = T pcb + (PQ x Rth )
5.8.9. Current Sensing Components
In addition to the RDS(ON) loss and gate charge loss, QH also has switching loss. The procedure to select QH is similar to the procedure for QL. First, assign 2-5% of the output power to be dissipated in the RDS(ON) of QH using the equation for QL above. As was done with QL, calculate the RMS current as follows:
Once the current sense method has been selected (Refer to Section 5.9, "Current Limit Threshold Selection,"), the components are selected as follows. When using the inductor DCR sensing method, the user must also select an R/C network comprised of R1 and CL (see Figure 16).
I toprms = I Lrms x D
Calculate a starting RDS(ON) as follows, in this example using 5%:
PQH = 0.05 x VOUT x I OUT
RDS ( ON ) =
(I
PQH
toprms
)
Figure 16. DCR Current Sensing
2
Select a MOSFET and calculate the resulting gate drive current. Verify that the combined gate drive current from QL and QH does not exceed 80 mA. Next, calculate the switching time using:
For the voltage across CL to reflect the voltage across the DCR of the inductor, the time constant of the inductor must match the time constant of the RC network. That is:
RC = L / DCR
L DCR
t SW =
Qg I gdr
R1 C L =
where Qg is the gate charge of the selected QH and Igdr is the peak gate drive current available from the ZL2008. Although the ZL2008 has a typical gate drive current of 3 A, use the minimum guaranteed current of 2 A for a conservative design. Using the calculated switching time, calculate the switching power loss in QH using:
For L, use the average of the nominal value and the minimum value. Include the effects of tolerance, DC Bias and switching frequency on the inductance when determining the minimum value of L. Use the typical value for DCR. The value of R1 should be as small as feasible and no greater than 5 k for best signal-to-noise ratio. The designer should make sure the resistor package size is appropriate for the power dissipated and include this loss in efficiency calculations. In calculating the minimum value of R1, the average voltage across CL (which is the average IOUTDCR product) is small and can be neglected. Therefore, the minimum value of R1 may be approximated by the following equation:
Pswtop = VINM x t sw x I OUT x f sw
The total power dissipated by QH is given by the following equation:
PQHtot = PQH + Pswtop
24
R1- min =
D (VIN - max - VOUT ) + (1 - D ) VOUT , PR1 pkg - max P
2 2
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
where PR1pkg-max is the maximum power dissipation specification for the resistor package and P is the derating factor for the same parameter (eg.: PR1pkg-max = 0.0625W for 0603 package, P = 50% @ 85C). Once R1-min has been calculated, solve for the maximum value of CL from additional efficiency losses incurred by devices that must use an additional series resistance in the circuit.
C L-max =
L R1- min DCR
and choose the next-lowest readily available value (eg.: For CL-max = 1.86uF, CL = 1.5uF is a good choice). Then substitute the chosen value into the same equation and re-calculate the value of R1. Choose the 1% resistor standard value closest to this re-calculated value of R1. The error due to the mismatch of the two time constants is
= 1 -
R2 = 5 R1
R1 C L DCR 100% Lavg
The value of R2 should be simply five times that of R1:
For the RDS(ON) current sensing method, the external low side MOSFET will act as the sensing element as indicated in Figure 17.
5.9 Current Limit Threshold Selection
Figure 17. Current Sensing Methods
It is recommended that the user include a current limiting mechanism in their design to protect the power supply from damage and prevent excessive current from being drawn from the input supply in the event that the output is shorted to ground or an overload condition is imposed on the output. Current limiting is accomplished by sensing the current through the circuit during a portion of the duty cycle. Output current sensing can be accomplished by measuring the voltage across a series resistive sensing element according to the following equation:
To set the current limit threshold, the user must first select a current sensing method. The ZL2008 incorporates two methods for current sensing, synchronous MOSFET RDS(ON) sensing and inductor DC resistance (DCR) sensing; Figure 17 shows a simplified schematic for each method. The current sensing method can be selected via the I2C/SMBus interface. Please refer to Application Note AN33 for details. In addition to selecting the current sensing method, the ZL2008 gives the power supply designer several choices for the fault response during over or under current condition. The user can select the number of violations allowed before declaring fault, a blanking time and the action taken when a fault is detected. The blanking time represents the time when no current measurement is taken. This is to avoid taking a reading just after a current load step (less accurate due to potential ringing). It is a configurable parameter. Once the sensing method has been selected, the user must select the voltage threshold (VLIM), the desired current limit threshold, and the resistance of the sensing element. The current limit threshold voltage can be selected by simply connecting the ILIM pin as shown in Table 18. The ground-referenced sensing method is being used in this mode.
Data Sheet Revision 2/19/2009 www.intersil.com
V LIM = I LIM x RSENSE
Where: ILIM is the desired maximum current that should flow in the circuit. RSENSE is the resistance of the sensing element. VLIM is the voltage across the sensing element at the point the circuit should start limiting the output current. The ZL2008 supports "lossless" current sensing by measuring the voltage across a resistive element that is already present in the circuit. This eliminates
25
ZL2008
Table 18. Current Limit Threshold Voltage Pin-strap Settings ILIM Pin Threshold Voltage LOW OPEN HIGH 50 mV 60 mV 70 mV
DPWM 1-D C RC RO
VIN
D L
VOUT
Table 19. Current Limit Threshold Voltage Resistor Settings RLIM VLIM RLIM VLIM 10 k 0 mV 34.8 k 65 mV 11 k 5 mV 38.3 k 70 mV 12.1 k 10 mV 42.2 k 75 mV 13.3 k 15 mV 46.4 k 80 mV 14.7 k 20 mV 51.1 k 85 mV 16.2 k 25 mV 56.2 k 90 mV 17.8 k 30 mV 61.9 k 95 mV 19.6 k 35 mV 68.1 k 100 mV 21.5 k 40 mV 75 k 105 mV 23.7 k 45 mV 82.5 k 110 mV 26.1 k 50 mV 90.9 k 115 mV 28.7 k 55 mV 100 k 120 mV 31.6 k 60 mV
Compensation
Figure 18. Control Loop Block Diagram
In the ZL2008, the compensation zeros and gain are set by configuring the FC0 and FC1 pins or via the I2C/SMBus interface once the user has calculated the required settings. This method eliminates the inaccuracies due to the component tolerances associated with using external resistors and capacitors required with traditional analog controllers. The compensation is configured using a baseline set of PID taps which are scaled on the factors of Gain, Q and Fn as shown in Table 20, Table 21 and Table 22. The parameters Gain, Q and Fn are defined in AN35 and are parameters of the compensator (not the power stage being compensated). The selection of these scaling factors is based on compensation required for additional output capacitance used in an application.
Table 20. FC0 Pin-strap Settings Gain Scale FC0 Pin (dB) -12 LOW OPEN HIGH 0 6 Q-new / Q-base 1
The threshold voltage can also be selected in 5 mV increments by connecting a resistor, RLIM, between the ILIM pin and ground according to Table 19. This method is preferred if the user does not desire to use or does not have access to the I2C/SMBus interface and the desired threshold value is contained in Table 19. The current limit threshold can also be set to a custom value via the I2C/SMBus interface. Please refer to Application Note AN33 for further details.
5.10 Loop Compensation
The ZL2008 operates as a voltage-mode synchronous buck controller with a fixed frequency PWM scheme. Although the ZL2008 uses a digital control loop, it operates much like a traditional analog PWM controller. Figure 18 is a simplified block diagram of the ZL2008 control loop, which differs from an analog control loop only by the constants in the PWM and compensation blocks. As in the analog controller case, the compensation block compares the output voltage to the desired voltage reference and compensation zeroes are added to keep the loop stable. The resulting integrated error signal is used to drive the PWM logic, converting the error signal to a duty cycle to drive the external MOSFETs.
Table 21. FC1 Pin-strap Settings FC1 Pin LOW OPEN HIGH 1 Fn-new / Fn-base
The scaling factors are applied to the baseline set of taps to achieve the desired compensation results. These baseline taps correspond to zeroes of the form:
2 s s + Gbase1 + (Qbase 2 fnbase) (Qbase * 2 fnbase)
Data Sheet Revision 2/19/2009 www.intersil.com
26
ZL2008
Where Gbase = 20 dB Qbase = 2 fnbase = fSW/10 Both the baseline taps and the calculated taps determined by the FC0 and FC1 resistors can be read via the I2C/SMBus interface. Please refer to Application Note AN33 for further details.
Table 22. Loop Compensation Resistor Settings RFC0 10 k 11 k 12.1 k 13.3 k 14.7 k 16.2 k 17.8 k 19.6 k 21.5 k 23.7 k 26.1 k 28.7 k 31.6 k 34.8 k 38.3 k 42.2 k 46.4 k 51.1 k 56.2 k 61.9 k 68.1 k 75 k 82.5 k 90.9 k 100 k 110 k 121 k 133 k 147 k 162 k 178 k -12 -6 0 6 12 Gain Scale (dB) Q-new / Q-base 0.6813 0.4642 0.3162 0.2154 0.1468 0.1000 0.6813 0.4642 0.3162 0.2154 0.1468 0.1000 0.6813 0.4642 0.3162 0.2154 0.1468 0.1000 1.0000 0.6813 0.4642 0.3162 0.2154 0.1468 0.1000 0.6813 0.4642 0.3162 0.2154 0.1468 0.1000 RFC1 10 k 11 k 12.1 k 13.3 k 14.7 k 16.2 k 17.8 k 19.6 k 21.5 k 23.7 k 26.1 k 28.7 k 31.6 k 34.8 k 38.3 k 42.2 k 46.4 k 51.1 k 56.2 k 61.9 k 68.1 k 75 k 82.5 k 90.9 k 100 k 110 k 121 k 133 k 147 k 162 k 178 k Fn-new / Fn-base 1.0000 0.9050 0.8190 0.7411 0.6707 0.6070 0.5493 0.4971 0.4498 0.4071 0.3684 0.3334 0.3017 0.2730 0.2471 0.2236 0.2024 0.1831 0.1657 0.1500 0.1357 0.1228 0.1112 0.1006 0.0910 0.0824 0.0745 0.0675 0.0611 0.0553 0.0500
27
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
5.11 Non-linear Response (NLR) Settings
The ZL2008 incorporates a non-linear response (NLR) loop that decreases the response time and the output voltage deviation in the event of a sudden output load current step. The NLR loop incorporates a secondary error signal processing path that bypasses the primary error loop when the output begins to transition outside of the standard regulation limits. This scheme results in a higher equivalent loop bandwidth than what is possible using a traditional linear loop. When a load current step function imposed on the output causes the output voltage to drop below the lower regulation limit, the NLR circuitry will force a positive correction signal that will turn on the upper MOSFET and quickly force the output to increase. Conversely, a negative load step (i.e. removing a large load current) will cause the NLR circuitry to force a negative correction signal that will turn on the lower MOSFET and quickly force the output to decrease. NLR can be configured using resistor pin-straps as follows: CFG0 disables NLR or enables NLR inner thresholds to 1.5%, 2% or 3% (see Table 34). CFG1 sets NLR inner thresholds timeout & blanking to 1 & 4 or 2 & 8 (see Table 31). Please refer to Application Note AN32 for more details regarding NLR settings.
5.12 Efficiency Optimized Driver Dead-time Control
D
VOUT VIN
However, non-idealities exist that cause the real duty cycle to extend beyond the ideal. Dead-time is one of those non-idealities that can be manipulated to improve efficiency. The ZL2008 has an internal algorithm that constantly adjusts dead-time nonoverlap to minimize duty cycle, thus maximizing efficiency. This circuit will null out dead-time differences due to component variation, temperature, and loading effects. This algorithm is independent of application circuit parameters such as MOSFET type, gate driver delays, rise and fall times and circuit layout. In addition, it does not require drive or MOSFET voltage or current waveform measurements.
5.13 Adaptive Diode Emulation
Most power converters use synchronous rectification to optimize efficiency over a wide range of input and output conditions. However, at light loads the synchronous MOSFET will typically sink current and introduce additional energy losses associated with higher peak inductor currents, resulting in reduced efficiency. Adaptive diode emulation mode turns off the low-side FET gate drive at low load currents to prevent the inductor current from going negative, reducing the energy losses and increasing overall efficiency. Diode emulation is available to single-phase devices only. Note: the overall bandwidth of the device may be reduced when in diode emulation mode. It is recommended that diode emulation is disabled prior to applying significant load steps.
5.14 Adaptive Frequency Control
The ZL2008 utilizes a closed loop algorithm to optimize the dead-time applied between the gate drive signals for the top and bottom FETs. In a synchronous buck converter, the MOSFET drive circuitry must be designed such that the top and bottom MOSFETs are never in the conducting state at the same time. Potentially damaging currents flow in the circuit if both top and bottom MOSFETs are simultaneously on for periods of time exceeding a few nanoseconds. Conversely, long periods of time in which both MOSFETs are off reduce overall circuit efficiency by allowing current to flow in their parasitic body diodes. It is therefore advantageous to minimize this dead-time to provide optimum circuit efficiency. In the first order model of a buck converter, the duty cycle is determined by the equation:
Since switching losses contribute to the efficiency of the power converter, reducing the switching frequency will reduce the switching losses and increase efficiency. The ZL2008 includes Adaptive Frequency Control mode, which effectively reduces the observed switching frequency as the load decreases.
28
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Adaptive frequency mode is enabled by setting bit 0 of MISC_CONFIG to 1 and is only available while the device is operating within Adaptive Diode Emulation Mode. As the load current is decreased, diode emulation mode decreases the GL on-time to prevent negative inductor current from flowing. As the load is decreased further, the GH pulse width will begin to decrease while maintaining the programmed frequency, fPROG (set by the FREQ_SWITCH command).
fSW(D) fPROG
Once the GH pulse width (D) reaches 50% of the nominal duty cycle, DNOM (determined by Vin and Vout), the switching frequency will start to decrease according to the following equation: If D <
DNOM then 2 2( fSW - fMIN ) D + fMIN fSW(D) = DNOM
Otherwise fSW(D) = fPROG This is illustrated in Figure 19. Due to quantizing effects inside the IC, the ZL2008 will decrease its frequency in steps between fSW and fMIN. The quantity and magnitude of the steps will depend on the difference between fSW and fMIN as well as the frequency range.
DNOM 2 D
fMIN 0
Duty Cycle
Figure 19. Adaptive Frequency
It should be noted that adaptive frequency mode is not available for current sharing groups and is not allowed when the device is placed in auto-detect mode and a clock source is present on the SYNC pin, or if the device is outputting a clock signal on its SYNC pin.
29
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
6. Power Management Functional Description
6.1 Input Undervoltage Lockout
The input undervoltage lockout (UVLO) prevents the ZL2008 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. The UVLO threshold (VUVLO) can be set between 2.85 V and 16 V using the UVLO pin. The simplest implementation is to connect the UVLO pin as shown in Table 23. If the UVLO pin is left unconnected, the UVLO threshold will default to 4.5 V.
Table 23. UVLO Threshold Pin-strap Settings UVLO Pin UVLO Threshold LOW OPEN HIGH 3V 4.5 V 10.8 V
The default response from a UVLO fault is an immediate shutdown of the device. The device will continuously check for the presence of the fault condition. If the fault condition is no longer present, the ZL2008 will be re-enabled. Please refer to Application Note AN33 for details on how to configure the UVLO threshold or to select specific UVLO fault response options via the I2C/SMBus interface.
6.2 Output Overvoltage Protection
If the desired UVLO threshold is not one of the listed choices, the user can configure a threshold between 2.85 V and 16 V by connecting a resistor between the UVLO pin and SGND by selecting the appropriate resistor from Table 24.
Table 24. UVLO Threshold Resistor Settings RUVLO UVLO RUVLO UVLO 17.8 k 2.85 V 46.4 k 7.42 V 19.6 k 3.14 V 51.1 k 8.18 V 21.5 k 3.44 V 56.2 k 8.99 V 23.7 k 3.79 V 61.9 k 9.9 V 26.1 k 4.18 V 68.1 k 10.9 V 28.7 k 4.59 V 75 k 12 V 31.6 k 5.06 V 82.5 k 13.2 V 34.8 k 5.57 V 90.9 k 14.54 V 38.3 k 6.13 V 100 k 16 V 42.2 k 6.75 V
The ZL2008 offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. A hardware comparator is used to compare the actual output voltage (seen at the VSEN pin) to a threshold set to 15% higher than the target output voltage (the default setting). If the VSEN voltage exceeds this threshold, the PG pin will deassert and the device can then respond in a number of ways as follows: 1. Initiate an immediate shutdown until the fault has been cleared. The user can select a specific number of retry attempts. 2. Turn off the high-side MOSFET and turn on the low-side MOSFET. The low-side MOSFET remains ON until the device attempts a restart. The default response from an overvoltage fault is to immediately shut down. The device will continuously check for the presence of the fault condition, and when the fault condition no longer exists the device will be re-enabled. For continuous overvoltage protection when operating from an external clock, the only allowed response is an immediate shutdown. Please refer to Application Note AN33 for details on how to select specific overvoltage fault response options via I2C/SMBus.
6.3 Output Pre-Bias Protection
The UVLO voltage can also be set to any value between 2.85 V and 16 V via the I2C/SMBus interface. Once an input undervoltage fault condition occurs, the device can respond in a number of ways as follows: 1. Continue operating without interruption. 2. Continue operating for a given delay period, followed by shutdown if the fault still exists. The device will remain in shutdown until instructed to restart. 3. Initiate an immediate shutdown until the fault has been cleared. The user can select a specific number of retry attempts.
An output pre-bias condition exists when an externally applied voltage is present on a power supply's output before the power supply's control IC is enabled. Certain applications require that the converter not be allowed to sink current during start up if a pre-bias condition exists at the output. The ZL2008 provides
Data Sheet Revision 2/19/2009 www.intersil.com
30
ZL2008
pre-bias protection by sampling the output voltage prior to initiating an output ramp. If a pre-bias voltage lower than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled. The output voltage is then ramped to the final regulation value at the ramp rate set by the SS pin. The actual time the output will take to ramp from the pre-bias voltage to the target voltage will vary depending on the pre-bias voltage but the total time elapsed from when the delay period expires and when the output reaches its target value will match the preconfigured ramp time. See Figure 20. If a pre-bias voltage higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled with a PWM duty cycle that would ideally create the pre-bias voltage. Once the pre-configured soft-start ramp period has expired, the PG pin will be asserted (assuming the prebias voltage is not higher than the overvoltage limit). The PWM will then adjust its duty cycle to match the original target voltage and the output will ramp down to the pre-configured output voltage.
Figure 20. Output Responses to Pre-bias Voltages
If a pre-bias voltage higher than the overvoltage limit exists, the device will not initiate a turn-on sequence and will declare an overvoltage fault condition to exist. In this case, the device will respond based on the output overvoltage fault response method that has been selected. See Section 6.2"Output Overvoltage Protection," for response options due to an overvoltage condition. Pre-bias protection is not offered for current sharing groups that also have tracking enabled.
31
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
6.4 Output Overcurrent Protection
The ZL2008 can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. Once the current limit threshold has been selected (see Section 5.9 "Current Limit Threshold Selection"), the user may determine the desired course of action in response to the fault condition. The following overcurrent protection response options are available: 1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. Continue operating for a given delay period, followed by shutdown if the fault still exists. 4. Continue operating through the fault (this could result in permanent damage to the power supply). 5. Initiate an immediate shutdown. The default response from an overcurrent fault is an immediate shutdown of the device. The device will continuously check for the presence of the fault condition, and if the fault condition no longer exists the device will be re-enabled. Please refer to Application Note AN33 for details on how to select specific overcurrent fault response options via I2C/SMBus.
6.5 Thermal Overload Protection
2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. Continue operating for a given delay period, followed by shutdown if the fault still exists. 4. Continue operating through the fault (this could result in permanent damage to the power supply). 5. Initiate an immediate shutdown. If the user has configured the device to restart, the device will wait the preset delay period (if configured to do so) and will then check the device temperature. If the temperature has dropped below a threshold that is approx 15 C lower than the selected temperature fault limit, the device will attempt to re-start. If the temperature still exceeds the fault limit the device will wait the preset delay period and retry again. The default response from a temperature fault is an immediate shutdown of the device. The device will continuously check for the fault condition, and once the fault has cleared the ZL2008 will be re-enabled. Please refer to Application Note AN33 for details on how to select specific temperature fault response options via I2C/SMBus.
6.6 Voltage Tracking
The ZL2008 includes an on-chip thermal sensor that continuously measures the internal temperature of the die and shuts down the device when the temperature exceeds the preset limit. The default temperature limit is set to 125 C in the factory, but the user may set the limit to a different value if desired. See Application Note AN33 for details. Note that setting a higher thermal limit via the I2C/SMBus interface may result in permanent damage to the device. Once the device has been disabled due to an internal temperature fault, the user may select one of several fault response options as follows: 1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts.
Numerous high performance systems place stringent demands on the order in which the power supply voltages are turned on. This is particularly true when powering FPGAs, ASICs, and other advanced processor devices that require multiple supply voltages to power a single die. In most cases, the I/O interface operates at a higher voltage than the core and therefore the core supply voltage must not exceed the I/O supply voltage according to the manufacturers' specifications. Voltage tracking protects these sensitive ICs by limiting the differential voltage between multiple power supplies during the power-up and power down sequence. The ZL2008 integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the VTRK pin with no external components required. The VTRK pin is an analog input that, when tracking mode is enabled, configures the voltage applied to the VTRK pin to act as a reference for the device's output regulation.
32
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
The ZL2008 offers two mode of tracking as follows: 1. Coincident. This mode configures the ZL2008 to ramp its output voltage at the same rate as the voltage applied to the VTRK pin. 2. Ratiometric. This mode configures the ZL2008 to ramp its output voltage at a rate that is a percentage of the voltage applied to the VTRK pin. The default setting is 50%, but an external resistor string may be used to configure a different tracking ratio. Figure 21 illustrates the typical connection and the two tracking modes. The master ZL2008 device in a tracking group is defined as the device that has the highest target output voltage within the group. This master device will control the ramp rate of all tracking devices and is not configured for tracking mode. A delay of at least 10 ms must be configured into the master device using the SS pin, and the user may also configure a specific ramp rate using the SS pin. Any device that is configured for tracking mode will ignore its soft-start delay and ramp time settings (SS pin) and its output will take on the turn-on/turn-off characteristics of the reference voltage present at the VTRK pin. All of the ENABLE pins in the tracking group must be connected together and driven by a single logic source. Tracking is configured via the I2C/SMBus interface by using the TRACK_CONFIG PMBus command. Please refer to Application Note AN33 for more information on configuring tracking mode using PMBus. It should be noted that current sharing groups that are also configured to track another voltage do not offer pre-bias protection; a minimum load should therefore be enforced to avoid the output voltage from being held up by an outside force. Additionally, a device set up for tracking must have both Alternate Ramp Control and Precise Ramp-Up Delay disabled.
VIN
GH Q1 L1 Q2
ZL
VTRK
SW GL
VOUT
C1
VTRK VOUT
VTRK
VOUT
Time
Coincident
VOUT
VTRK
VOUT
Time
Ratiometric
Figure 21. Tracking Modes
Table 25. Tracking Resistor Settings Track Ratio Upper Track Limit RSS 90.9 k Limited by target 100 k 100% 110 k Limited by VTRK 121 k 133 k Limited by target 147 k 50% 162 k Limited by VTRK 178 k
Ramp-up/down Behavior Output does not decrease before PG Output always follows VTRK Output does not decrease before PG Output always follows VTRK Output does not decrease before PG Output always follows VTRK Output does not decrease before PG Output always follows VTRK
33
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
6.7 Voltage Margining 6.9 I2C/SMBus Device Address Selection
The ZL2008 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. The MGN command is set by driving the MGN pin or through the I2C/SMBus interface. The MGN pin is a tri-level input that is continuously monitored and can be driven directly by a processor I/O pin or other logiclevel output. The ZL2008's output will be forced higher than its nominal set point when the MGN command is set HIGH, and the output will be forced lower than its nominal set point when the MGN command is set LOW. Default margin limits of VNOM 5% are preloaded in the factory, but the margin limits can be modified through the I2C/SMBus interface to as high as VNOM + 10% or as low as 0 V, where VNOM is the nominal output voltage set point determined by the V0 and V1 pins. A safety feature prevents the user from configuring the output voltage to exceed VNOM + 10% under any conditions. The margin limits and the MGN command can both be set individually through the I2C/SMBus interface. Additionally, the transition rate between the nominal output voltage and either margin limit can be configured through the I2C interface. Please refer to Application Note AN33 for detailed instructions on modifying the margining configurations.
6.8 I2C/SMBus Communications
When communicating with multiple SMBus devices using the I2C/SMBus interface, each device must have its own unique address so the host can distinguish between the devices. The device address can be set according to the pin-strap options listed in Table 26. Address values are right-justified.
Table 26. SMBus Address Pin-strap Selection SA0 LOW OPEN HIGH LOW 0x20 0x21 0x22 SA1 OPEN 0x23 0x24 0x25 HIGH 0x26 0x27 Reserved
If additional device addresses are required, a resistor can be connected to the SA0 pin according to Table 27 to provide up to 25 unique device addresses. In this case, the SA1 pin should be tied to SGND.
Table 27. SMBus Address Resistor Selection SMBus SMBus RSA0 RSA0 Address Address 10 k 0x00 34.8 k 0x0D 11 k 0x01 38.3 k 0x0E 12.1 k 0x02 42.2 k 0x0F 13.3 k 0x03 46.4 k 0x10 14.7 k 0x04 51.1 k 0x11 16.2 k 0x05 56.2 k 0x12 17.8 k 0x06 61.9 k 0x13 19.6 k 0x07 68.1 k 0x14 21.5 k 0x08 75 k 0x15 23.7 k 0x09 82.5 k 0x16 26.1 k 0x0A 90.9 k 0x17 28.7 k 0x0B 100 k 0x18 31.6 k 0x0C
The ZL2008 provides an I2C/SMBus digital interface that enables the user to configure all aspects of the device operation as well as monitor the input and output parameters. The ZL2008 can be used with any standard 2-wire I2C host device. In addition, the device is compatible with SMBus version 2.0 and includes an SALRT line to help mitigate bandwidth limitations related to continuous fault monitoring. Pull-up resistors are required on the I2C/SMBus as specified in the SMBus 2.0 specification. The ZL2008 accepts most standard PMBus commands. When controlling the device with PMBus commands, it is recommended that the enable pin is tied to SGND.
If more than 25 unique device addresses are required or if other SMBus address values are desired, both the SA0 and SA1 pins can be configured with a resistor to SGND according to the following equation and Table 28.
SMBus address = 25 x (SA1 index) + (SA0 index) (in decimal)
34
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Table 28. SMBus Address Index Values SA0 or SA0 or SA1 RSA RSA SA1 Index Index 10 k 34.8 k 0 13 11 k 38.3 k 1 14 12.1 k 42.2 k 2 15 13.3 k 46.4 k 3 16 14.7 k 51.1 k 4 17 16.2 k 56.2 k 5 18 17.8 k 61.9 k 6 19 19.6 k 68.1 k 7 20 21.5 k 75 k 8 21 23.7 k 82.5 k 9 22 26.1 k 90.9 k 10 23 28.7 k 100 k 11 24 31.6 k 12
minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that will ensure a logic 0 (typically 0.8 V at the device monitoring point) given the pull-up voltage (5 V if tied to VR) and the pull-down current capability of the ZL2008 (nominally 4 mA).
6.11 Phase Spreading
Using this method, the user can theoretically configure up to 625 unique SMBus addresses, however the SMBus is inherently limited to 128 devices so attempting to configure an address higher than 128 (0x80) will cause the device address to repeat (i.e., attempting to configure a device address of 129 (0x81) would result in a device address of 1). Therefore, the user should use index values 0-4 on the SA1 pin and the full range of index values on the SA0 pin, which will provide 125 device address combinations.
6.10 Digital-DC Bus
When multiple point of load converters share a common DC input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. Setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. Since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the IRMS2 are reduced dramatically. In order to enable phase spreading, all converters must be synchronized to the same switching clock. The CFG1 pin is used to set the configuration of the SYNC pin for each device as described in Section 5.7 "Switching Frequency and PLL" on Page 20. The phase offset of each single-phase device may be set to any value between 0 and 337.5 in 22.5 increments using the CFG2 pin as shown in Table 29 and Table 30.
Table 29. Phase Offset Pin-strap Settings CFG2 Pin Phase Offset LOW OPEN HIGH 90 0 180
The Digital-DC Communications (DDC) bus is used to communicate between Zilker Labs Digital-DC devices. This dedicated bus provides the communication channel between devices for features such as sequencing, fault spreading, and current sharing. The DDC pin on all Digital-DC devices in an application should be connected together. A pull-up resistor is required on the DDC bus in order to guarantee the rise time as follows: Rise time = RPU * CLOAD 1 s, where RPU is the DDC bus pull-up resistance and CLOAD is the bus loading. The pull-up resistor may be tied to VR or to an external 3.3 V or 5 V supply as long as this voltage is present prior to or during device power-up. As rules of thumb, each device connected to the DDC bus presents approx 10 pF of capacitive loading, and each inch of FR4 PCB trace introduces approx 2 pF. The ideal design will use a central pull-up resistor that is well-matched to the total load capacitance. In power module applications, the user should consider whether to place the pull-up resistor on the module or on the PCB of the end application. The
35
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Table 30. Phase Offset Resistor Settings Phase Offset RCFG2 22.5 10 k 45.0 11 k 67.5 12.1 k 90.0 13.3 k 112.5 14.7 k 135.0 16.2 k 157.5 17.8 k 180.0 19.6 k 202.5 21.5 k 225.0 23.7 k 247.5 26.1 k 270.0 28.7 k 292.5 31.6 k 315.0 34.8 k 337.5 38.3 k
The sequencing group will turn on in order starting with the device with the lowest SMBus address and will continue through to turn on each device in the address chain until all devices connected have been turned on. When turning off, the device with the highest SMBus address will turn off first followed in reverse order by the other devices in the group. Sequencing is configured by connecting a resistor from the CFG1 pin to ground as described in Table 31. The CFG1 pin is also used to set the configuration of the SYNC pin as well as to determine the sequencing method and order. Please refer to 5.7 "Switching Frequency and PLL" for more details on the operating parameters of the SYNC pin. Multiple device sequencing may also be achieved by issuing PMBus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. This method places fewer restrictions on SMBus address (no need of sequential address) and also allows the user to assign any phase offset to any device irrespective of its SMBus device address. The Enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. Enable must be driven low to initiate a sequenced turnoff of the group. Refer to Application Note AN33 for details on sequencing via the I2C/SMBus interface.
6.13 Fault Spreading
The phase offset of (multi-phase) current sharing devices is automatically set to a value between 0 and 337.5 in 22.5 increments as described in Section 6.15. The phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments via the I2C/SMBus interface. Refer to Application Note AN33 for further details.
6.12 Output Sequencing
A group of Digital-DC devices may be configured to power up in a predetermined sequence. This feature is especially useful when powering advanced processors, FPGAs, and ASICs that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up from occurring. Multi-device sequencing can be achieved by configuring each device through the I2C/SMBus interface or by using Zilker Labs patented autonomous sequencing mode. Autonomous sequencing mode configures sequencing by using events transmitted between devices over the DDC bus. This mode is not available on current sharing rails. The sequencing order is determined using each device's SMBus address. Using autonomous sequencing mode (configured using the CFG1 pin), the devices must be assigned sequential SMBus addresses with no missing addresses in the chain. This mode will also constrain each device to have a phase offset according to its SMBus address as described in Section 6.11 "Phase Spreading".
Digital DC devices can be configured to broadcast a fault event over the DDC bus to the other devices in the group. When a non-destructive fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the DDC bus. The other devices on the DDC bus will shut down together if configured to do so, and will attempt to re-start in their prescribed order if configured to do so.
6.14 Temperature Monitoring Using the XTEMP Pin
The ZL2008 supports measurement of an external device temperature using either a thermal diode integrated in a processor, FPGA or ASIC, or using a discrete diode-connected 2N3904 NPN transistor. Figure 22 illustrates the typical connections required.
36
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Active Current Sharing
Paralleling multiple ZL2008 devices can be used to increase the output current capability of a single power rail. By connecting the DDC pins of each device together and configuring the devices as a current sharing rail, the units will share the current equally within a few percent. Figure 22 illustrates a typical connection for three devices. The ZL2008 uses a low-bandwidth, first-order digital current sharing technique to balance the unequal device output loading by aligning the load lines of member devices to a reference device. Droop resistance is used to add artificial resistance in the output voltage path to control the slope of the load line curve, calibrating out the physical parasitic mismatches due to power train components and PCB layout.
Figure 22. External Temperature Monitoring 6.15
Table 31. Sequencing Pin-strap and Resistor Settings RCFG1 LOW OPEN HIGH 10 k 11 k 12.1 k 14.7 k 16.2 k 17.8 k 21.5 k 23.7 k 26.1 k 31.6 k 34.8 k 38.3 k 46.4 k 51.1 k 56.2 k 68.1 k 75 k 82.5 k 100 k 110 k 121 k 147 k 162 k 178 k SYNC Pin Config Input Auto detect Output Input Auto detect Output Input Auto detect Output Input Auto detect Output Input Auto detect Output Input Auto detect Output Input Auto detect Output Input Auto detect Output Input Auto detect Output Sequencing Configuration Sequencing is disabled. NLR Timeout & Blanking 1&4
Sequencing is disabled. The ZL2008 is configured as the first device in a nested sequencing group. Turn on order is based on the device SMBus address. The ZL2008 is configured as a last device in a nested sequencing group. Turn on order is based on the device SMBus address. The ZL2008 is configured as the middle device in a nested sequencing group. Turn on order is based on the device SMBus address. Sequencing is disabled. The ZL2008 is configured as the first device in a nested sequencing group. Turn on order is based on the device SMBus address. The ZL2008 is configured as a last device in a nested sequencing group. Turn on order is based on the device SMBus address. The ZL2008 is configured as the middle device in a nested sequencing group. Turn on order is based on the device SMBus address.
1&4
2&8
37
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
3.3V - 5V
VIN
CIN
DDC
ZL
COUT
The ISHARE_CONFIG command is used to configure the device for active current sharing. The default setting is a stand-alone non-current sharing device. A current sharing rail can be part of a system sequencing group. For fault configuration, the current share rail is configured in a quasi-redundant mode. In this mode, when a member device fails, the remaining members will continue to operate and attempt to maintain regulation. Of the remaining devices, the device with the lowest member position will become the reference. If fault spreading is enabled, the current share rail failure is not broadcast until the entire current share rail fails. Up to eight (8) devices can be configured in a given current sharing rail.
Table 32. Current Share Position Settings RCFG2 Current Share Position 0 42.2 k 1 46.4 k 2 51.1 k 3 56.2 k 4 61.9 k 5 68.1 k 6 75 k 7 82.5 k
CIN
DDC
ZL
COUT
VOUT
CIN
DDC
ZL
COUT
Figure 23. Current Sharing Group
VOUT
Figure 24. Active Current Sharing
Upon system start-up, the device with the lowest member position as selected in ISHARE_CONFIG is defined as the reference device. The remaining devices are members. The reference device broadcasts its current over the DDC bus. The members use the reference current information to trim their voltages (VMEMBER) to balance the current loading of each device in the system. Figure 24 shows that, for load lines with identical slopes, the member voltage is increased towards the reference voltage which closes the gap between the inductor currents. The relation between reference and member current and voltage is given by the following equation:
Table 33. Current Share Pin-strap Settings Current CFG0 Current Share # of NLR Pin Sharing Members LOW OPEN HIGH 1.5% Disabled 2% 0 Disabled
VMEMBER = VOUT + R x (I REFERENCE - I MEMBER )
where R is the value of the droop resistance.
38
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Table 34. Current Share Resistor Settings Current Current Share # of NLR RCFG0 Sharing Members 10 k 11 k 12.1 k 13.3 k 14.7 k 16.2 k 17.8 k 19.6 k 21.5 k 23.7 k 26.1 k 28.7 k 31.6 k 34.8 k 38.3 k 42.2 k 46.4 k 51.1 k 56.2 k 61.9 k 68.1 k 75 k 82.5 k 90.9 k 100 k 110 k 121 k 133 k 147 k 162 k 178 k 3% 2 3 4 5 6 7 8 0 2 3 4 5 6 7 8 0 2 3 4 5 6 7 8 0 2 3 4 5 6 7 8 Enabled 6.16 Phase Adding/Dropping
Disabled
Enabled
The ZL2008 allows multiple power converters to be connected in parallel to supply higher load currents than can be addressed using a single-phase design. In doing so, the power converter is optimized at a load current range that requires all phases to be operational. During periods of light loading, it may be beneficial to disable one or more phases in order to eliminate the current drain and switching losses associated with those phases, resulting in higher efficiency. The ZL2008 offers the ability to add and drop phases using a the phase enable pin or a PMBus command in response to an observed load current change. All phases in a current share rail are considered active prior to the current sharing rail ramp to power-good. Phases can be dropped after power-good is reached. The phase enable pin can be used to drop and add phases: * * Set PH_EN = 0 to drop a phase Set PH_EN = 1 to add a phase
Disabled
Disabled
The time to detect a change of state of the phase enable pin is between 0 ms and 3 ms (max).
Enabled
2%
Any member of the current sharing rail can be dropped. If the reference device is dropped, the remaining active device with the lowest member position will become the new reference. Additionally, any change to the number of members of a current sharing rail will precipitate autonomous phase distribution within the rail where all active phases realign their phase position based on their order within the number of active members. If the members of a current sharing rail are forced to shut down due to an observed fault, all members of the rail will attempt to re-start simultaneously after the fault has cleared. For single phase operation, that is, not current sharing, the PH_EN pin is ignored and can be left open.
Disabled
1.5%
Enabled
The phase offset of (multi-phase) current sharing devices is automatically set to a value between 0 and 337.5 in 22.5 increments as follows:
Phase Offset = SMBus Address[4:0] - Current Share Position * 22.5
Please refer to Application Note AN34 for additional details on current sharing.
39
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
6.17 Monitoring via I2C/SMBus Table 35. Snapshot Parameters Byte Description 31:22 Reserved 21:20 Vin 19:18 Vout 17:16 Iout,avg 15:14 Iout,peak 13:12 Duty cycle 11:10 Internal temp 9:8 External temp 7:6 fsw 5 Vout status 4 Iout status 3 Input status 2 Temp status 1 CML status 0 Mfr specific status Format Linear Linear Vout Linear Linear Linear Linear Linear Linear Linear Byte Byte Byte Byte Byte Byte
A system controller can monitor a wide variety of different ZL2008 system parameters through the I2C/SMBus interface. The device can monitor for fault conditions by monitoring the SALRT pin, which will be pulled low when any number of pre-configured fault conditions occur. The device can also be monitored continuously for any number of power conversion parameters including but not limited to the following: * * * * * Input voltage / Output voltage Output current Internal and external temperature Switching frequency Duty cycle
The PMBus Host should respond to SALRT as follows: 1. ZL device pulls SALRT Low 2. PMBus Host detects that SALRT is now low, performs transmission with Alert Response Address to find which ZL device is pulling SALRT low. 3. PMBus Host talks to the ZL device that has pulled SALRT low. The actions that the host performs are up to the System Designer. If multiple devices are faulting, SALRT will still be low after doing the above steps and will require transmission with the Alert Response Address repeatedly until all faults are cleared. Please refer to Application Note AN33 for details on how to monitor specific parameters via the I2C/SMBus interface.
6.18 Snapshot Parameter Capture
The SNAPSHOT_CONTROL command enables the user to store the snapshot parameters to Flash memory in response to a pending fault as well as to read the stored data from Flash memory after a fault has occurred. Table 36 describes the usage of this command. Automatic writes to Flash memory following a fault are triggered when any fault threshold level is exceeded, provided that the specific fault's response is to shut down (writing to Flash memory is not allowed if the device is configured to re-try following the specific fault condition). It should also be noted that the device's VDD voltage must be maintained during the time when the device is writing the data to Flash memory; a process that requires between 7001400 s depending on whether the data is set up for a block write. Undesirable results may be observed if the device's VDD supply drops below 3.0 V during this process.
Table 36. SNAPSHOT_CONTROL Command Data Value 1 Description Copies current SNAPSHOT values from Flash memory to RAM for immediate access using SNAPSHOT command. Writes current SNAPSHOT values to Flash memory. Only available when device is disabled.
The ZL2008 offers a special feature that enables the user to capture parametric data during normal operation or following a fault. The Snapshot functionality is enabled by setting bit 1 of MISC_CONFIG to 1. The Snapshot feature enables the user to read the parameters listed in Table 35 via a block read transfer through the SMBus. This can be done during normal operation, although it should be noted that reading the 22 bytes will occupy the SMBus for some time.
2
In the event that the device experiences a fault and power is lost, the user can extract the last SNAPSHOT parameters stored during the fault by writing a 1 to SNAPSHOT_CONTROL (transfers data from Flash memory to RAM) and then issuing a SNAPSHOT command (reads data from RAM via SMBus).
Data Sheet Revision 2/19/2009 www.intersil.com
40
ZL2008
6.19 Non-Volatile Memory and Device Security Features
The ZL2008 has internal non-volatile memory where user configurations are stored. Integrated security measures ensure that the user can only restore the device to a level that has been made available to them. Refer to Section 5.4 "Start-up Procedure," for details on how the device loads stored values from internal memory during start-up. During the initialization process, the ZL2008 checks for stored values contained in its internal non-volatile memory. The ZL2008 offers two internal memory storage units that are accessible by the user as follows: 1. Default Store: A power supply module manufacturer may want to protect the module from damage by preventing the user from being able to modify certain values that are related to the physical construction of the module. In this case,
the module manufacturer would use the Default Store and would allow the user to restore the device to its default setting but would restrict the user from restoring the device to the factory settings. 2. User Store: The manufacturer of a piece of equipment may want to provide the ability to modify certain power supply settings while still protecting the equipment from modifying values that can lead to a system level fault. The equipment manufacturer would use the User Store to achieve this goal. Please refer to Application Note AN33 for details on how to set specific security measures via the I2C/SMBus interface.
41
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
7. Pin-strap Current Sharing Configuration
A 3-phase current sharing group example is shown in Figure 25. Each ZL2008 device in the group is connected to the same DDC bus and SMBus. Also, the enable pins are connected together to allow all devices in the current sharing group to enable simultaneously. The device with the lowest position number becomes the reference device. The reference device provides the load current information to each member device. If the reference device is dropped or faults then the device with the next lowest position number will become the new reference device.
3.3V VCC
b. Current Share Control - Current sharing is automatically enabled when the number of members is 2 (and disabled when members is = 0). Resistor pin-strap the CFG2 pin to set the following parameter: c. Current Share Position - Sequential numbering from 0 to 7 (max) of N number of members starting with the reference device in position 0 and ending with the last member device in position N-1. For the 3-phase group the parameters for each device are shown in Table 37.
Table 37. Current Share Parameters
Device SMBus Address 0x20 0x21 0x22 # of Members 3 3 3 Position 0 1 2 Control Enabled Enabled Enabled
DEV_1 0x20 REF. POS_0 POS_1
DDC SDA SCL SYNC SYNC_Out VCC
Rail_1 Rail DDC ID = 5
Rout Cout
PH_1
DEV_2 0x21 MEM_1 POS_2 POS_1 PH_2
Reference Member_1 Member_2
SYNC_In VCC
7.3 SYNC Clock (CFG1 Pin)
DEV_3 0x22 MEM_2 POS_3 POS_2 PH_3
SYNC_In
Figure 25. 3-phase Current Sharing Group
Typically the reference device sources the SYNC clock. However, any device internal or external to the current sharing group can source the SYNC clock. If the reference device is sourcing the SYNC clock, then resistor pin-strap the CFG1 pin to configure the SYNC pin as an output. Otherwise configure the reference device's SYNC pin as an input. For member devices, resistor pin-strap the CFG1 pin to configure the SYNC pin as an input.
7.4 Soft Start (SS Pin)
7.1 SMBus Address (SA0, SA1 Pins)
Assign sequential SMBus addresses to each device in the current sharing group. If other non-current sharing devices are connected to the same SMBus then assign addresses to these devices that are before or after the current sharing group.
7.2 Current Share Pin-Straps (CFG0, CFG2 Pins)
Current sharing groups require proper synchronization prior to ramp events. Resistor pin-strap the SS pin to set the following parameters: a. Delay Time - The reference device's soft start delay time must be at least 10 ms greater than any member device to ramp up/down current sharing. The reference device requires this additional time to coordinate a synchronization signal to all member devices. b. Ramp Time - A minimum soft start ramp time of 5 ms is required for both reference and member devices to ramp up/down current sharing.
Data Sheet Revision 2/19/2009 www.intersil.com
Resistor pin-strap the CFG0 pin to set the following parameters: a. Current Share # of Members - Number of devices or phases in a current sharing group (2 minimum and 8 maximum).
42
ZL2008
7.5 Phase Enable (PH_EN Pin)
Phase enable is used to dynamically add or drop a current sharing phase during operation. Set the PH_EN pin high to enable a phase and low to disable a phase (open is an invalid state). The PH_EN pin replaces the PHASE_CONTROL command. For proper operation, the pin must be externally driven high or low without switching glitches. Also, ensure phase enable is high for the reference and member devices of a current sharing group prior to ramp-up.
7.6 MFR_CONFIG Command
Selection,"). The same sensing is used for both reference and member devices. Note, the following parameters are automatically set when current sharing is enabled. c. Alternate Ramp Control (bit 2) - Automatically set to "1" (enabled) for both reference and member devices when current sharing is enabled. d. SYNC Pin Output Control (bit 0) - Automatically set to push-pull for a SYNC clock output and open-drain for a SYNC clock input.
Table 38. Current Sense Options Current Sense Configuration Ground referenced, down slope (RDSON sensing) Vout referenced, down slope (Inductor DCR sensing) Vout referenced, up slope (Inductor DCR sensing) 7.7 VOUT_DROOP Command Usage Low duty cycle and low fSW Low duty cycle and high fSW High duty cycle
Application specific values are set by the MFR_CONFIG command. The following parameters must be set to properly configure current sharing. a. Current Sense Blanking Delay (bits 15:11) - The current sense delay parameter controls the blanking time when no current measurement is taken. This allows the filtering of noise from the current measurement circuit when the FETs are switching. The actual value selected depends on fSW, sensing method and ring-out duration. The same delay is used for both reference and member devices. b. Current Sense Control (bits 5:4) - Three modes of current sensing are available depending on duty cycle and switching frequency as listed in Table 38. (Also refer to Section 5.9, "Current Limit Threshold
The droop or load-line resistance is used as part of the current sharing algorithm. When current sharing is enabled, VOUT_DROOP is automatically set to a value of 0xBA80 (1.25 m). The same droop value is used for both reference and member devices.
43
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Table 39. Pin-Strap Current Sharing Resistor Values Pin Reference Member_1 Member_2 SA0, SA1 CFG0 CFG1 CFG2 Low, Low 23.7 k High 42.2 k Open, Low 23.7 k Low 46.4 k High, Low 23.7 k Low 51.1 k Description SMBus Address = 0x20 for Reference SMBus Address = 0x21 for Member_1 SMBus Address = 0x22 for Member_2 Current Share # of Members = 3 Current Share Control = Enabled SYNC = Output for Reference SYNC = Input for Member_1 and Member_2 Current Share Position = 0 for Reference Current Share Position = 1 for Member_1 Current Share Position = 2 for Member_2 Delay = 15 ms, Ramp = 5 ms for Reference Delay = 5 ms, Ramp = 5 ms for Member_1 Delay = 5 ms, Ramp = 5 ms for Member_2 All Phases Enabled
SS PH_EN
31.6 k High
14.7 k High
14.7 k High
7.8 Current Sharing Example
Example pin-strap resistor values for the current sharing group in Figure 25 are shown in Table 39. Sequential SMBus addresses are used with the reference device at the lowest address. The reference device outputs the SYNC clock to the member devices SYNC clock input. The devices are configured for 3phase current sharing with all phases enabled. The reference device soft start ramp time is at least 5 ms and soft start delay time is at least 10 ms greater than the member devices for proper synchronization and output voltage ramp.
44
1-888-INTERSIL or 1-888-468-3774|Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners
ZL2008
8. Package Dimensions
Notes: 1. Dim ensions a nd tolera nces conf orm to ASME Y1 4 . 5 M - 1 9 9 4 . 2. 3. 4. All dim ensions a re in m illim eters, is in degrees. N is the tota l num ber of term ina ls. Dim ension b a pplies to m eta liz ed term ina l a nd is m ea sured between 0 . 1 5 a nd 0 . 3 3 m m f rom term ina l tip. If the term ina l ha s the optiona l ra dius on the other end of the term ina l, the dim ension b should not be m ea sured in tha t ra dius a rea . ND a nd NE ref er to the num ber of term ina ls on ea ch D a nd E side respectively. Ma x pa ck a ge wa rpa ge is 0 . 0 5 m m . Ma xim um a llowa ble burrs is 0 . 0 7 6 m m in a ll directions. Pin # 1 ID on top will be la ser m a rk ed. Bila tera l copla na rity z one a pplies to the exposed hea t sink slug a s well a s the term ina ls. This dra wing conf orm s to JEDEC registered outline MO- 2 2 0 .
S
YM
DIMENSIONS
BO L
N
MIN. 0 .8 0 0 .0 0 0
NOM.
MAX.
O T
E
A A1 A3
k D E e N ND NE L b D2 E2
5. 6. 7. 8. 9. 10.
0.8 5 0.9 0 0.0 2 0.0 5 0 . 2 0 REF 12 0 . 2 0 MIN 6 . 0 BSC 6 . 0 BSC 0 . 5 0 BSC 36 9 9 0.6 0 0.2 5 4.1 0 4.1 0 0.6 5 0.3 0 4.2 0 4.2 0
2
3 5 5 4
0 .5 5 0 .1 8 4 .0 0 4 .0 0
45
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
9. Ordering Information
10. Related Tools and Documentation
The following application support documents and tools are available to help simplify your design.
Item Description
AN10 AN32 AN33 AN34 AN35
Application Note: Thermal and Layout Guidelines Application Note: NLR Configuration Application Note: PMBus Command Set Application Note: Current Sharing Application Note: Compensation Using CompZL
11. Revision History
Rev. # Description Date
1.0
Initial release
January 2009 February 2009
Assigned file number FN6859 to datasheet as this will be the first release with an Intersil file number. Replaced header and footer with Intersil header and footer. FN6859.0 Updated disclaimer information to read "Intersil and it's subsidiaries including Zilker Labs, Inc." No changes to datasheet content
46
Data Sheet Revision 2/19/2009 www.intersil.com
ZL2008
Zilker Labs, Inc. 4301 Westbank Drive Building A-100 Austin, TX 78746
Tel: 512-382-8300 Fax: 512-382-8329
(c) 2009, Zilker Labs, Inc. All rights reserved. Zilker Labs, Digital-DC, Snapshot, and the Zilker Labs Logo are trademarks of Zilker Labs, Inc. All other products or brand names mentioned herein are trademarks of their respective holders. This document contains information on a product under development. Specifications are subject to change without notice. Pricing, specifications and availability are subject to change without notice. Please see www.zilkerlabs.com for updated information. This product is not intended for use in connection with any high-risk activity, including without limitation, air travel, life critical medical operations, nuclear facilities or equipment, or the like. The reference designs contained in this document are for reference and example purposes only. THE REFERENCE DESIGNS ARE PROVIDED "AS IS" AND "WITH ALL FAULTS" AND INTERSIL CORPORATION AND IT'S SUBSIDIARIES INCLUDING ZILKER LABS, INC. DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS OR IMPLIED. ZILKER LABS SHALL NOT BE LIABLE FOR ANY DAMAGES, WHETHER DIRECT, INDIRECT, CONSEQUENTIAL (INCLUDING LOSS OF PROFITS), OR OTHERWISE, RESULTING FROM THE REFERENCE DESIGNS OR ANY USE THEREOF. Any use of such reference designs is at your own risk and you agree to indemnify Intersil Corporation and it's subsidiaries including Zilker Labs, Inc. for any damages resulting from such use.
47
Data Sheet Revision 2/19/2009 www.intersil.com

▲Up To Search▲

Price & Availability of ZL2008ALAFT

	To Download ZL2008ALAFT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .